A Review of Processor Design Flow

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A Review of Processor Design Flow
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How to design a CPU ?

• Instruction-set architecture (ISA) design
• Function-level (RTL) design
• Component-level design
• Gate-level/switch-level design
• Circuit-level design

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Design Method

• Gate Level/circuit level toward full CAD
• Register Level CAD heuristics/intuition
• ISA Level mainly heuristic process
• with simulation validation

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Design Levels of Abstraction
Abstract
Architecture
Logic
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LAYOUT
Concrete
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Design Levels and Component Types
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Classical ISA Level Design Method

• Select a prototype structure A
• Modify A to accommodate
• new performance demand and new technology
• Evaluation (ISA simulation)
• Repeating until satisfaction

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Overall Simulation Strategy

• Instruction level simulator this is used for
  performance evaluation at the instruction set
  level as well as for more detailed modeling, e.g.
  the pipeline and memory system. This level is
  also used to generate test vectors employed in
  lower-level simulators.
• System level simulation this simulator models
  the details of the system environment including
  such things as interrupts and memory management.
• (Virtual machine level ..)

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Overall Simulation Strategy
(Cond)

• 3. RTL level this simulator models are RTL
  description of the design
• Switch level with delays used to simulate the
  design mostly in components test vectors are
  generated from the RTL level.
• 5. Circuit simulation it is used for detailed
  modeling of the critical paths as well as for
  verification of circuits under variations in
  temperature, power supply, etc.

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Performance of Simulators
of cycles simulated per second on a host machine
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Instruction Set Architecture Simulation
Runtime statistics (frequencies, cycle counts,
etc.)
Execution -driven simulator
Object file
Profile information
Traces (e.g. memory accesses branch trace, etc.)
Architecture Models
Trace-driven simulator (cache simulator branch
prediction simulator, etc.)
Statistics (e.g. cache behavior, branch behavior,
etc.)
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Performance Study by Simulation

• Develop performance model that is
• Flexible
• Parameterized (via knobs)
• 95 clock accurate compared to RTL
• Significantly smaller than RTL
• Models consist of two parts
• Instruction-set simulator -gt executes benchmark
• Pipeline simulator -gt accountant for clock
  cycles
• Run benchmarks, update microarchitecture
  accordingly
• Cycle of code -gt simulate -gt characterize -gt
  tune

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Revisit How to design a CPU ?

• Instruction-set architecture (ISA) design
• Function-level (RTL) design
• Component-level design
• Gate-level/switch-level design
• Circuit-level design

Monty Denneau I work on everything down to and
including 4. Cyclops skips (2) and goes directly
to 3/4. A lot of time was spent restructuring
the design to make 4 meet timing. I probably
spent thousands of hours on 4. We have no 5 -
ASICS provides a library of gates, latches, and
memory, etc. August 28, 2007