Prabhat Mishra, Nikil Dutt, Alex Nicolau

1

• Prabhat Mishra, Nikil Dutt, Alex Nicolau
• Architectures and Compilers for Embedded Systems
  (ACES)
• Center for Embedded Computer Systems
• University of California, Irvine
• November 8, 2001

2
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

3
Traditional HW/SW Co-Design Flow
Design Specification
Estimation
HW/SW Partitioning
HW VHDL, Verilog
SW C
Synthesis
Compilation
Co-Simulation
Off-Chip Memory
Processor Core
On-Chip Memory
Synthesized HW
Interface
4
ADL-Driven SOC Design Flow
Design Specification
ADL Specification
Estimation
HW/SW Partitioning
HW VHDL, Verilog
SW C
Synthesis
Compilation
Co-Simulation
ADL Architecture Description Language
Off-Chip Memory
On-Chip Memory
Processor Core
Synthesized HW
Interface
5
ADL-Driven SOC Design Flow
Design Specification
ADL Specification
Estimation
HW/SW Partitioning
Is specification correct?
HW VHDL, Verilog
SW C
Synthesis
Compilation
Co-Simulation
Goal To ensure the correctness of
the software toolkit
Off-Chip Memory
On-Chip Memory
Processor Core
Synthesized HW
Interface
6
ADL-Driven SOC Design Flow
Design Specification
ADL Specification
Estimation
HW/SW Partitioning
Verification
HW VHDL, Verilog
SW C
Synthesis
Compilation
Well-formed Specification
Co-Simulation
Off-Chip Memory
On-Chip Memory
Processor Core
Synthesized HW
Interface
7
ADL-driven Validation Flow
Processor IP Library
Processor Core
Feedback
ADL Specification
Properties
Verified
Graph Model
Failed
Compiler
Simulator
Obj
Application
8
The EXPRESSION ADL

• The EXPRESSION ADL is used for specifiying
  processor-memory architectures.
• Compiler and simulator are generated
• The ADL captures
• structure
• behavior
• mapping
• pipeline path
• data-trasnfer path

9
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
10
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
11
Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Fetch, Read1, ALU, Read2, Shift, WB is a
pipeline path
12
Data-transfer Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
P2
Shift
ACC
o
WB
P1
C1
WB, P1, C1, P2, RegFile is a data-transfer path
13
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
14
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
15
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
16
The EXPRESSION Description of DLX Architecture
Structure
(ARCHITECTURE_SECTION ..........
(FetchUnit FETCH (CAPACITY 4) (TIMING
(all 1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT F2DLatch)) ) ) (PIPELINE_SECTION
(PIPELINE FETCH DECODE Execute MEM WB) (Execute
(ALTERNATE IALU MUnit FAdd FDiv)) (MUnit
(PIPELINE M1 M2 M3 M4 M5 M6 M7)) (FAdd
(PIPELINE FADD1 FADD2 FADD3 FADD4)) (DTPATHS
(TYPE UNI (REGFILE DECODE p7 c4 p8)
(WRITEBACK REGFILE p5 c3 p6) ) (TYPE BI
(MEM MEMORY p4 c2 p3) ) )
17
The EXPRESSION Description of DLX Architecture
Structure
Behavior
(OPCODE DIV (OPERANDS (SRC1 rf) (SRC2 im)
(DEST rf)) (BEHAVIOR DEST SRC1/SRC2) )
18
The EXPRESSION Description of DLX Architecture
Structure
Mapping
Behavior
(OPCODE DIV (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1/SRC2) )
19
Verification of Processor Pipeline

• Verify that the model of the architecture
  satisfies the properties
• Connectedness
• False Pipeline Path
• Completeness
• Well-formedness
• Finiteness

20
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

21
Connectedness Property
Each component must be accessed by at least one
pipeline path or data-transfer path.
Fetch
Algorithm
Input 1. Graph model of the processor
2. ListOfUnits, ListOfPorts,
ListOfConnections, .. Output True, if each
component can be accessed by at
least one pipeline path or data-transfer path 1.
Unmark all the entries in all the input lists 2.
Traverse each unit u of the graph G starting from
the root I. Mark unit u in ListOfUnits
ii. For each output latch l of u mark the latch
in ListOfLatches iii. For each port p of u
mark the port in ListOfPorts For
each connection c from port p mark the
connection in ListOfConnections
For each port q on c (! p) mark the port in
ListOfPorts 3. Return false if there are any
unmarked entries else true.
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
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Connectedness Property
Each component must be accessed by at least one
pipeline path or data-transfer path.
Fetch
Algorithm
Input 1. Graph model of the processor
2. ListOfUnits, ListOfPorts,
ListOfConnections, .. Output True, if each
component can be accessed by at
least one pipeline path or data-transfer path 1.
Unmark all the entries in all the input lists 2.
Traverse each unit u of the graph G starting from
the root I. Mark unit u in ListOfUnits
ii. For each output latch l of u mark the latch
in ListOfLatches iii. For each port p of u
mark the port in ListOfPorts For
each connection c from port p mark the
connection in ListOfConnections
For each port q on c (! p) mark the port in
ListOfPorts 3. Return false if there are any
unmarked entries else true.
C1
P1
o
Read1
ALU
MUL
P2
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
23
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

24
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Supports two operations alus (ALU-shift) and mac
(multiply-accumulate)
25
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Four pipeline paths Fetch, Read1, ALU, Read2,
Shift, WB alus
Fetch, Read1, MUL, Read2, ACC, WB
Fetch, Read1, ALU,
Read2, ACC, WB
Fetch, Read1, MUL, Read2, Shift, WB
26
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Four pipeline paths Fetch, Read1, ALU, Read2,
Shift, WB alus
Fetch, Read1, MUL, Read2, ACC, WB mac
Fetch, Read1,
ALU, Read2, ACC, WB
Fetch, Read1, MUL, Read2, Shift, WB
27
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Four pipeline paths Fetch, Read1, ALU, Read2,
Shift, WB alus
Fetch, Read1, MUL, Read2, ACC, WB mac
Fetch, Read1,
ALU, Read2, ACC, WB
Fetch, Read1, MUL, Read2, Shift, WB
28
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Four pipeline paths Fetch, Read1, ALU, Read2,
Shift, WB alus
Fetch, Read1, MUL, Read2, ACC, WB mac
Fetch, Read1,
ALU, Read2, ACC, WB
Fetch, Read1, MUL, Read2, Shift, WB
29
False Pipeline Path
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Four pipeline paths Fetch, Read1, ALU, Read2,
Shift, WB alus
Fetch, Read1, MUL, Read2, ACC, WB mac
Fetch, Read1,
ALU, Read2, ACC, WB X
Fetch, Read1, MUL, Read2, Shift,
WB X
False pipeline paths
30
False Pipeline Path
Algorithm
Input Graph model of the processor with each
functional unit u having its list
of supported opcodes, Supp_u Output True, if the
graph model satisfies the property else
false. 1. Traverse each unit u of the graph G
starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
Read1
ALU
MUL
Read2
Shift
ACC
WB
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
31
False Pipeline Path
Algorithm
Input 1. Graph model of the processor with
each functional unit u having
its list of supported opcodes, Supp_u Output
True, if the graph model satisfies the property
else false. 1. Traverse each unit u of the graph
G starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
InL alus, mac SopL alus, mac OutL alus,
mac
Read1
ALU
MUL
Read2
Shift
ACC
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
WB
32
False Pipeline Path
Algorithm
Input 1. Graph model of the processor with
each functional unit u having
its list of supported opcodes, Supp_u Output
True, if the graph model satisfies the property
else false. 1. Traverse each unit u of the graph
G starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
InL alus, mac SopL alus, mac OutL alus,
mac
Read1
ALU
MUL
InL alus, mac SopL mac OutL mac
Read2
Shift
ACC
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
WB
33
False Pipeline Path
Algorithm
Input 1. Graph model of the processor with
each functional unit u having
its list of supported opcodes, Supp_u Output
True, if the graph model satisfies the property
else false. 1. Traverse each unit u of the graph
G starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
InL alus, mac SopL alus, mac OutL alus,
mac
Read1
ALU
MUL
InL alus, mac SopL mac OutL mac
InL mac SopL alus, mac OutL mac
Read2
Shift
ACC
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
WB
34
False Pipeline Path
Algorithm
Input 1. Graph model of the processor with
each functional unit u having
its list of supported opcodes, Supp_u Output
True, if the graph model satisfies the property
else false. 1. Traverse each unit u of the graph
G starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
InL alus, mac SopL alus, mac OutL alus,
mac
Read1
ALU
MUL
InL alus, mac SopL mac OutL mac
InL mac SopL alus, mac OutL mac
Read2
Shift
ACC
InL mac SopL alus OutL
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
WB
35
False Pipeline Path
Algorithm
Input 1. Graph model of the processor with
each functional unit u having
its list of supported opcodes, Supp_u Output
True, if the graph model satisfies the property
else false. 1. Traverse each unit u of the graph
G starting from the root I. Root node sends
Supp_root to its children OutList_root
Supp_root ii. Each node j the InList_j is
the same as the OutList_i where i is the parent
of j. iii. Each node j computes the
OutList_j by performing intersection with
InList_j and its supported opcodes and sends the
OutList_j to its children iv. If OutList_j
is NULL the function returns false path error and
enumerates the path. 2. Return true if there are
no false pipeline paths.
InL SopL alus, mac OutL alus, mac
Fetch
InL alus, mac SopL alus, mac OutL alus,
mac
Read1
ALU
MUL
InL alus, mac SopL mac OutL mac
InL mac SopL alus, mac OutL mac
Read2
Shift
ACC
InL Input List OutL from the parent SopL
List of supported opcodes OutL Output list
Intersection of InL and SopL
InL mac SopL alus OutL
WB
Fetch, Read1, MUL, Read2, Shift, WB is a false
pipeline path
36
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

37
Completeness
Algorithm
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports the operation op ii. For each
op and each pp that supports op a.
Check if there are nodes where operands are read
in correct order b. Check if there is
node where result is written back c.
Check if there is a path from read nodes to write
nodes. 2. Return false if there are operations
which are not executable.
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Each operation must be executable there should
be at least one pipeline path that supports the
operation
38
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports the operation op ii. For each
op and each pp that supports op a.
Check if there are nodes where operands are read
in correct order b. Check if there is
node where result is written back c.
Check if there is a path from read nodes to write
nodes. 2. Return false if there are operations
which are not executable.
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Each operation must be executable there should
be at least one pipeline path that supports the
operation
39
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports the operation op ii. For each
op and each pp that supports op a.
Check if there are nodes where operands are read
in correct order b. Check if there is
node where result is written back c.
Check if there is a path from read nodes to write
nodes. 2. Return false if there are operations
which are not executable.
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Each operation must be executable there should
be at least one pipeline path that supports the
operation
40
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports op ii. For each op and each pp
that supports op a. Check if there are
nodes where operands are read in correct order
b. Check if there is node where result is
written back c. Check if there is a path
from read nodes to write nodes. 2. Return false
if there are operations which are not executable.
Fetch
o
Read1
ALU
MUL
o
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Each operation must be executable there should
be at least one pipeline path that supports the
operation
41
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports op ii. For each op and each pp
that supports op a. Check if there are
nodes where operands are read in the correct
order. b. Check if there is node where
result is written back c. Check if there
is a path from read nodes to write nodes. 2.
Return false if there are operations which are
not executable.
Fetch
R1, R2
o
Read1
ALU
MUL
o
R3
o
Reg File
o
Read2
o
Shift
ACC
o
WB
Each operation must be executable there should
be at least one pipeline path that supports the
operation
42
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports op ii. For each op and each pp
that supports op a. Check if there are
nodes where operands are read in correct order
b. Check if there is node where result is
written back c. Check if there is a path
from read nodes to write nodes. 2. Return false
if there are operations which are not executable.
Fetch
R1, R2
o
Read1
ALU
MUL
o
R3
o
Reg File
o
Read2
o
Shift
ACC
o
WB
R4
Each operation must be executable there should
be at least one pipeline path that supports the
operation
43
Completeness
Algorithm
alus R4 (R1 R2) ltlt R3 mac R4 (R1 R2)
R3
Input 1. Graph model of the processor G
2. ListOfOperations supported by the
Output True, if the graph model satisfies the
property else false. 1. For each operation oper
with opcode op I. Identify pipeline paths pp
which supports op ii. For each op and each pp
that supports op a. Check if there are
nodes where operands are read in correct order
b. Check if there is node where result is
written back c. Check if there is a path
from read nodes to write nodes. 2. Return false
if there are operations which are not executable.
Fetch
R1, R2
o
Read1
ALU
MUL
o
R3
o
Reg File
o
Read2
o
Shift
ACC
o
WB
R4
Each operation must be executable there should
be at least one pipeline path that supports the
operation
44
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

45
Well-formedness

• The number of operations processed per cycle
  cannot be smaller than the total number of
  operations sent by its parents.
• There should be a path from branch unit to
  PC/Fetch unit
• The instruction template should match available
  pipeline bandwidth.

46
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

47
Finiteness

• Termination of the pipeline must be guaranteed.
• All pipeline paths (except false paths) should be
  of finite length
• Each unit should have finite timing
• Cannot be determined in the presence of cycles
• Necessary to verify that stalls are resolved in a
  finite number of cycles.

48
Outline

• Motivation
• ADL-driven Validation Flow
• The EXPRESSION ADL
• Verification of Processor Pipeline
• Connectedness
• False pipeline path
• Completeness
• Well-formedness
• Finiteness
• Experiments
• Summary and Future Work

49
Experiments

• Described MIPS R10K, TIC6x, PowerPC, DLX, and ARM
  processors using EXPRESSION ADL.
• Generated the graph model automatically.
• Applied the properties on the graph model.
• The complete validation of each processor
  specification took less than a second on a 295
  MHz Sun Ultra 60 with 1024M RAM

50
Experiments
1. Encountered two kinds of errors incomplete
specification incorrect specification 2.
Encountered many incorrect specification errors
during design space exploration of architectures
51
Summary

• Important to validate pipeline specification to
  ensure the correctness of the software toolkit
• Present an automatic validation framework
• Generate graph model from the ADL description of
  the processor.
• Defined necessary properties to ensure that the
  architecture is well-formed.
• Applied these properties on the graph model.
• Applied this methodology on pipeline
  specification of MIPS R10K, TI C6x, PowerPC, DLX,
  and ARM processors.

52
Future Work

• Extend the technique to validate the
  specification of memory subsystem and
  co-processors along with processor description.
• Verify the execution style (e.g., in-order) of
  the specified architecture using finite-state
  machine based modeling of the pipelined
  architecture.

53

• Thank you!

54
Architecture Description Languages

• Behavior-Centric ADLs
• ISPS, nML, ISDL, SCP/ValenC, ...
• primarily capture Instruction Set (IS)
• good for regular architectures, provides
  programmers view
• tedious for irregular architectures, hard to
  specify pipelining
• Structure-Centric ADLs
• MIMOLA, ...
• primarily capture architectural structure
• specify pipelining drive code generation, arch.
  synthesis
• hard to extract IS view
• Mixed-Level ADLs
• LISA, RADL, FLEXWARE, MDes, EXPRESSION,
• combine benefits of both
• generate simulator and/or compiler