FPGA Applications in HPC

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FPGA Applications in HPC

• Topics from the Technical Symposium on
  Reconfigurable Computing with FPGAs
• 21-22 February 2005, Michael Smith Building

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What is an FPGA?

• Field Programmable Gate Array - Array of
  programmable logic gates - Shares lineage with
  ASIC and CPLD - Gates arranged to form logic
  elements - Gates' configuration is booted from
  memory - Reconfigurable board layout is
  dynamic
• Slower clock than current CPUs lt 500 MHz
• High IO/memory bandwidth 11 Gb/s

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FPGA Internals

• Interconnected array of Logic Blocks
• Interconnect and gates user-programmable
• Complexity of design limited only by number of
  gates

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Relevance to HPC

• Inherent parallelism
• Replication of logic components gives many
  operations per cycle - 10x speedup common -
  Even higher for particular uses
• Integrates with existing systems
• Technology old, but has crossed usefulness
  threshold...

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FPGAs Today

• 90 nm manufacturing process - Increasing gate
  density - Decreasing cost
• Integration routes
• Mature development environment
• Identified application areas

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Prospects

• Less 'transistors' than current CPUs
• Moore's law has different implications for CPUs
  and FPGA
• 2002 62K gates
• 2004 6M gates
• 2006 - ?

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Systems Integration

• Co-processor atavism
• Dense computational kernel of code offloaded to
  FPGA - Small region of code - Suited to
  representation in FPGA - High proportion of
  execution time

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Integration

• From PCI board...
• ...to Cray XD-1 - 12 Opterons - 6 FPGA
• Dedicated proximal memory for FPGAs - QDR
  SRAM - Mapped to VM
• Embedded PowerPC

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Development

• 'Drag and Drop' development using GUI
• Reduces to HDL layout
• Verilog/VHDL
• C-like languages
• API and profiling tools - SpeedShop - GDB

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HPC Algorithms

• Existing algorithms ported to FPGA - Matrix
  algebra - FFT - Raytracing - Pattern
  matching
• Benchmarks show linear relationship between gate
  usage and performance
• Application-specific cores

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Application Areas

• Integer operations / Bitstream - DSP - DNA
  analysis - Cryptography / Cryptanalysis - XOR,
  multiplication modulo 216, c... - 130x
  speedup
• FPGAs historically showed poor floating-point
  performance - Legacy of limited gate area -
  Resolved by increased gate count

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Adaptive Optics (i)

• Durham University
• Atmospheric turbulence correction
• Hard real-time - High sampling freq. -
  Real-time deformation - No postprocessing

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Adaptive Optics (ii)

• Must scale to next-generation telescopes
• From Beowulf to Cray XD-1
• FPGAs 'essential' to scalability of solution

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FPGA Caveats

• Floating-point performance
• Requires access to data! - Bound by interconnect
  bandwidth - Mitigated by dedicated SRAM
• Scheduling - Embedded PowerPC CPU - CPU as FPGA
  supervisor
• NASA HC-36 and travelling-salesman

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Summary

• New category of high performance computer(?)
• Major industry support - Cray - SGI - Xilinx,
  Altera and developers
• Reconfigurable computing allows new paradigms
  - Core rotation in situ (Mars Rovers) -
  Hardware or Software?
• Integration and development challenges

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