A%20Graph-Partitioning-Based%20Approach%20for%20Multi-Layer%20Constrained%20Via%20Minimization

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A Graph-Partitioning-Based Approach for
Multi-Layer Constrained Via Minimization

• Yih-Chih Chou and Youn-Long Lin
• Department of Computer Science, Tsing Hua
  University, Hsin-Chu, Taiwan, R.O.C.

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Outline

• Introduction
• Constrained via minimization problem
• Layer Assignment Algorithm
• Special consideration
• Experimental Flow and Results
• Conclusions and Future Work

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Introduction

• Side effect of vias
• Chip area, Performance, Yield, Reliability
• Via minimization problem
• Two layer CVM, Multi-layer CVM
• Problem transformation
• Practical consideration

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Basic Terminology

• Net
• Via
• Stacked via
• Mutually exclusive wire segments
• Connected wire segments

metal1
metal1
1
metal2
M3
Net 2
Net 1
M2
2
metal2
M1
metal3
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Constrained Via Minimization (CVM)

• CVM-K problem
• n wire segments
• k different layers
• feasible assignment lt gt (
  )
• all design rules must be satisfied

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Graph representation--G( )

• Exclusive edge
• Connected edge
• Partitioning
• Cut
• Via Count

5
M1
10
9
M2
3
4
M3
2
8
6
1
7
1
M3
3
4
8
9
10
7
5
2
6
M2
M1
exclusive
connected
Node partitioning
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Problem Formulation

• Feasible partitioning
• Problem Transformation
• Quality of partitioning
• Feasible move
• K-way graph-partitioning problem

M2
M2
M2
M1
M1
M1
2
a
2
2
1
1
1
b
M3
M3
M3
3
4
a valid edge b invalid edge
feasible move
infeasible move
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Feasible Partitioning with Illegal Via
Net 2
metal 1
1
M2
M1
M3
Net 1
3
1
2
3
Net 1
2
Illegal via for metal 1 and metal 3
metal 2
metal 3
connected
exclusive
Net 2
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Layer Assignment Algorithm

• Simulated Annealing-based Optimization
• Modification
• Random selection
• Sequential evaluation

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Simultaneous Movement
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Via Counting
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Via Counting Example

metal 3
An example of via counting
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An Observation
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Metal 2
Metal 1
6
5
4
Metal 2
1
6
4
3
2
5
7
3
1
Metal 3
Metal 1
Metal 3
2
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Via Updating

• Partial modification
• An example

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Special Consideration

• Overlap consideration
• I/O pin limitation
• Over-the-cell constraint

Net 2
a1
Net 1
a1
a2
a2
Net 1
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Experimental Flow
Input
Cell Library
Technology Mapping (SIS)
Verilog-In automatic PR Edif-Out
Edif Parser
Our algorithm with interlock solution
Our algorithm w/o interlock solution
Result
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Experimental Results
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Conclusions

• Formulating CVM-K problem as a constrained k-way
  graph partitioning problem
• Modified simulated annealing based heuristic
• High reduction ratio
• Apply to large circuits
• More effective than standard simulated annealing
  method

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Future Work

• Crosstalk reduction
• Delay minimization
• Antenna Effect Consideration