??? (Youn-Long Lin)

1
High-Level Synthesis of VLSIs

• ??? (Youn-Long Lin)
• Department of Computer Science
• National Tsing Hua University

THEDA Tsing Hua Electronic Design Automation
2
VLSI Design Tools

• Design Capturing/Entry
• Analysis and Characterization
• Synthesis/Optimization
• Physical (Floor planning, Placement, Routing)
• Logic (FSM, Retiming, Sizing, DFT)
• High Level(RTL, Behavioral)
• Management

3
Design Methodology Progress
Capture and Simulate
4
Why not Synthesis?
Why Synthesis?
Productivity
Performance Loss
Correctness
Unsynthesizability
Re-Targetability
Inertial
5
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
Xtor
GDSII
Placement
Y-Chart Dan D Gajski
Floorplan
Physical
6
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
Xtor
GDSII
Placement
Layout Synthesis
Floorplan
Physical
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Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
Xtor
GDSII
Placement
Logic Synthesis
Floorplan
Physical
8
Structural
Behavioral
Block
Algorithm
FSM
RTL
Boolean
Gate
Xtor
GDSII
Placement
High-Level Synthesis
Floorplan
Physical
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High Level Synthesis
Behavioral Description
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What Went Wrong?

• Too much emphasis on incremental work on
  algorithms and point tools
• Unrealistic assumption on component capability,
  architectures, timing, etc
• Lack of quality-measurement from the low level
• Too much promising on fully automation (silicon
  compiler??)

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Essential Issues

• Behavioral Specification Languages
• Target Architectures
• Intermediate Representation
• Operation Scheduling
• Allocation/Binding
• Control Generation

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Behavioral Specification Languages

• Add hardware-specific constructs to existing
  languages
• HardwareC
• Popular HDL
• Verilog, VHDL
• Synthesis-oriented HDL
• UDL/I

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Target Architectures

• Bus-based
• Multiplexer-based
• Register file
• Pipelined
• RISC, VLIW
• Interface Protocol

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Design Space Exploration
Delay
Arch I
Arch II
Arch III
Area
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FSM with Data Path (FSMD)
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Intermediate Representation



Data Flow Graph
Control Flow Graph
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Scheduling (Temporal Binding)

• Time Resource Tradeoff
• Time-Constrained
• Integer Linear Programming (ILP)
• Force-Directed
• Resource-Constrained
• List Scheduling
• Other Heuristics
• Simulated Annealing, Tabu Search, ...

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Allocation/Binding
19
(No Transcript)
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Controller Specification Generation
Scheduled CDFG
Allocated Datapath
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HLS Quality Measures

• Performance
• Area Cost
• Power Consumption
• Testability
• Reusability

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Hardware Variations

• Functional Units
• Pipelined, Multi-Cycle, Chained, Multi-Function
• Storage
• Register, RF, Multi-Ported, RAM, ROM, FIFO,
  Distributed
• Interconnect
• Bus, Segmented Bus, Mux, Protocol-Based

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Functional Unit Variations



Step 1





Step 2

-
Step 3
Step 4
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Storage/Interconnect Variations
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Architectural Pipelining
FSM
Data Path
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THEDAs Work on HLS

• ILP-based Scheduling
• Bipartite Weighted Matching for Datapath
  Allocation
• Performance-Driven Interconnect Synthesis
• Loop Folding Retiming
• Integrating Synthesis and Layout
• DSP Core Generation
• Book on HLS

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Integer Linear Programming for Scheduling

• Given Control Steps
• ASAP ALAP gt Possible Steps for each
  Operations
• Tight Constraints on
• Dependency
• One Scheduled Step per Op
• Resource Usage per Step
• Many Extensions

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Advanced Scheduling for Loop Folding
1
1
2
2
3
3
1 iteration per 3 cycles
1 iteration per 2 cycles
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Loop Folding(cont.)
1
2
3
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Retiming and Loop Folding
B
A
C
D
E
F
B
A
C
D
E
F
E
A
C
E
B
A
C
D
F
B
D
F
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Integrating Layout and Synthesis
HDL Description
PR
RC Extraction Delay Calculation
HDL Synthesis
Soft-Macro Formation
Soft-Macro Formation
Post-Layout Timing Analysis
Block Placement
Timing Ok no more area improvement
No
Soft-Macro Placement
Soft-Macro Placement
Module Resynthesis
Module Resynthesis
Chip Layout
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HLS Techniques for DSP Code Generation
Memory Allocation
Scheduling
Address Generation
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Applications of HLS Technology

• Code generation for embedded processors
• Retargetable compilers for application-specific
  instruction-set processors (ASIP)
• Reconfigurable computing
• Advanced features in logic synthesizer

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System-on-a-Chip
Processor
Memory
Wireless
Bridge
External Memory Interface
USB
IP
Bus Master
UART
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SOC with PLDs
Processor
Memory
Wireless
Bridge
External Memory Interface
USB
FPGA
Bus Master
FPGA
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System Houses/ IC Vendors (Fabless)
Wafer Foundry
Library/ IP Vendors (Chipless)
Integrators
EDA Vendors
Paradigm Shift
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IP and Synthesis

• Authoring IP for Synthesis
• Synthesis utilizing IP
• Synthesizing IPs

Executable Data Sheets
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Executable Data Sheets
More than just the Port Interface
IP Wrapper
IP
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Future Directions

• Realistic Methodology
• Evolutional Transition from Current Practice
• Domain Specific
• IP-Centric
• As both Authoring Aid and Integrator
• Software
• Co-design and Code Generation

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IC
Value
IP
EDA
Time