Hardware Design Environment

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Hardware Design Environment
Instructors Fu-Chiung Cheng (???) Associate
Professor Computer Science Engineering Tatung
University
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Outline

• Hardware Design Environment
• System Design Process
• Hardware Simulation
• Synthesis Process

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Hardware Design Environment

• As the size and complexity of digital systems
• more computer-aided design (CAD) tool are
• introduced into the hardware design processed.
• The widespread use of Hardware description
• languages (HDL) is no more than a decade old.
• More and more tools and technologies for digital
• system design are coming

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Digital System Design Process
Figure 1.1 (page 2) Design Idea gt Behavioral
Design gt Pseudo Code .. gt Data Path Design
gt Bus Register Structure gt Logic Design
gt Gate Wirelist, Netlist gt Physical Design
gt Transistor List, Layout, ... gt
Manufacturing gt Chip or Board
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Digital System Design Process

• Top-down design process
• Starting with a design idea
• Generating a chip or board

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Data path Design Phase
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Full Adder (Gate network)
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Full Adder (Verilog)
timescale 1 ns / 1 ns // A 6-gate full adder
this is a comment module fulladder (s, co, a, c,
c) // Port declarations output s, co input a,
b, c // Intermediate wires wire w1, w2, w3,
w4 // Netlist description xor (16, 12) g1 (w1,
a, b) xor (16, 12) g5 (s, w1, c) and (12, 10)
g2 (w2, c, b) and (12, 10) g3 (w3, c, a) and
(12, 10) g4 (w4, b, a) or (12, 10) g6 (co, w2,
w3, w4) endmodule
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Hardware simulation
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Verify Each Stage
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Hardware Simulation
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VerifyeachDesignStage
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Simulating an XOR
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Oblivious simulation.
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Event driven simulation.
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Categories of synthesis tools
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Synthesis process.
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Resource sharing.
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Testing

• Digital System Design Issues
• Simulation
• Synthesis
• Test and Testability
• Test and Testability
• Test generation
• Fault simulation
• Test bench programs

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Levels of abstractionThree common models

• Behavior
• Dataflow
• Structural

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Behavioral Description

• Most abstract
• Describe functions in procedural form
• Good for
• fast simulation of complex hardware units,
• verification and functional simulation of design
  idea
• modeling standard components and documentation
• Detail of hardware is unknown

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Dataflow Description

• Concurrent representation of the flow and
  movement of data
• Not good for end-user or non-technical document
• Good for designer for describe components to be
  synthesized
• Examples Self-timed library

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Structural Description

• Lowest and most detailed level of hardware
  description
• Good for hardware synthesis
• Contain a list of concurrently active components
  and their interconnection
• Gate-level description
• Timing simulation (OK)