Hybrid Conditional Sum/Carry Lookahead Adder.

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Hybrid Conditional Sum/Carry Lookahead Adder.

• by
• Stephen Malchi

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Project objective

• To design a low power high performance adder
• Sub micron technology
• Power is the main concern

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Conditional Sum Adder

• Generates individual sum and carry bits.
• Selects the true output based on the carry of
  previous stage.

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8-bit CSA Block diagram
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Hybrid CS/CLA
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Theoretical Delay

• Conditional Sum Adder
• T (log2n 1).2? 18?
• Hybrid Adder
• producing gs and ps 1?
• producing internal carries 2?
• 3 ? 4 12 ?

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Design

• Verilog gate level simulated and verified for
  functionality using Modelsim.

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Design Styles

• Static CMOS
• CPL (Complementary Pass Transistor Logic)
• Most efficient pass transistor logic
• Small input load and good output driving
  capability
• Reto Zimmermann and wolfgang Fichtner, Low-
  Power Logic Styles CMOS versus Pass-Transistor
  Logic

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CPL gates
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Simulation Result

• Static CPL

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Conclusion

• Hybrid Adder performance is better
• The advantages of CPL are restricted by the swing
  restoration circuitry
• Static is a better choice than CPL.
• Conditional Carry adder
• Reduces the MUX count by half in turn saves power
  and increases speed.

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References

• 1 Behrooz Parhami Computer Arithmetic
  Algorithms and Hardware Designs.
• 2 Kuo-Hsing Cheng, Shu-Min Chiang and Shun
  Wen Cheng The Improvement of Conditional Sum
  Adder for Lower Power Applications.
• 3 J.Slansky, Conditional Sum Addition logic.
  IRE Trans. Electron Computer. VOL EC-9 (1960).

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References cont.

• 4 Reto Zimmermann and wolfgang Fichtner, Low-
  Power Logic Styles CMOS versus Pass-Transistor
  Logic.