Andrzej Rucinski

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ECE668 Fundamentals of Computer Engineering
Module III Computer Aided Design
Andrzej Rucinski Spring 2004
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Overview

• Introduction to Computer Aided Design
• Electronic Design Automation
• Hardware Design Methodology
• EDA Solutions to Hardware Design
• Programmable Logic FPGA/PLD
• VLSI design for ASIC
• Mentor Graphics EDA Suite
• FPGA ASIC Design Flow

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Introduction CAD Definition

• Computer aided design is the modeling of physical
  systems on computers, allowing both interactive
  and automatic analysis of design variants, and
  the expression of designs in a form suitable for
  manufacturing.
• CAD systems are no more than computer programs
  (although often large and complex), using
  specialized computing hardware. The software
  normally comprises a number of different elements
  or functions that process the data stored in the
  database in different ways

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Electronic Design Automation

• The aim of CAD is to apply computers to both the
  modeling and communication of Electronic designs.
  
• An integrated circuit is a microelectronic
  semiconductor device consisting of many
  interconnected transistors and other components
• EDA Collaborative Software tools used for the
  development of Integrated Circuits and Systems.
• Examples of Companies selling EDA tools Mentor,
  Cadence, Intergraph, Synopsis etc..

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Hardware Design Methodology

• Very important, exists at every hardware
  manufacturer
• Iterative
• Design Process
• Problem definition need a clear, concise
  English statement
• System Requirements created from problem
  definition
• Reliability
• Cost
• Weight
• Power consumption
• Physical size
• Performance (Speed)
• Maintainability
• Compatibility with existing designs

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System Partitioning

• Break into manageable subsystems, each to be
  designed by teams of engineers
• Subsystem must be easy to handle
• Based on hardware performance requirements
  propagation delay or
• Based on reliability requirements
• For example, in an industry like Aerospace..
• Flight-critical
• Mission-critical
• Convenience-functions

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Hardware Concept Development

• Create several candidate designs
• High-level analysis
• Analyze each candidate architecture
• Reliability estimate
• Cost estimate
• Weight estimate
• Testability estimate
• Power estimate
• Eliminate some candidate designs
• PROBLEM Need detailed information to get
  reliable estimates

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Hardware and Software Specifications

• Detailed plan for a design that can meet certain
  requirements
• Hardware software design analysis
• Carry out for each candidate design that survived
  High-Level Analysis
• Keep analyzing designs as they are filled out to
  make sure that they meet system requirements
• Testing Design for Testability
• Search for faults of all types
• Design mistakes
• Implementation mistakes
• Component defects

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System Integration and Test

• Combine hardware software in a system prototype
• Example software that never created problems on
  a hardware emulator may cause problems on the
  actual hardware
• Usually due to assumptions coded in the emulator
  that are not fulfilled by the actual hardware

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EDA Solutions for Hardware Design

• Programmable Devices - FPGA/PLDs
• IC Design and Verification ASICs
• Embedded Systems Embedded Compilers
• Design for Test Testability and Synthesis debug
• PCB Motherboards, Microcontrollers
• Harness Systems Complex Electrical Wiring
  combined with Mechanical Elements
• Functional Verification Verification of highly
  complex Digital, Analog Mixed Signal SOCs.

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Programmable Logic FPGA/PLD

• FPGA Field Programmable Gate Arrays
• FPGAs are a class of programmable logic devices.
  They feature a gate-array-like architecture with
  a matrix of logic cells surrounded by a periphery
  of I/O cells.
• HDL Languages popularly used to program
  FPGAs/CPLDs are VHDL and Verilog.
• For prototyping, testing and verification of any
  digital design, FPGA is a very feasible testing
  device

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FPGA Design Flow

• FPGA Design Flow (Integrated Design Solution)
• Design Creation Manage Create and Analyze
  Complex Designs
• IP Integration of various FPGA Intellectual
  Property Cores
• Simulation Simulation of Complex Design
  regardless of Platform or Language
• Design and Analysis Enable faster debug for
  productivity
• Synthesis Improve Quality of results with faster
  Synthesis

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VLSI IC Design for ASIC

• ASIC Application Specific Integrated Circuit
• ASICs are integrated Circuits designed to perform
  a particular function by defining the
  interconnection of a set of basic circuit
  building blocks drawn from a library provided by
  the Circuit Manufacturer. Example Mentors ADK
  (ASIC Design Kit).
• ASICs are not re-programmable. They are the final
  product of the Integrated Circuit Design cycle.
• ASICs are cheaper when produced in Mass volumes
• ASICs are faster than FPGAs because they are
  custom built.

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ASIC Design Details

• Specifications
• Concept design
• System specification
• CAD Inputs (Mentor, Verilog, Compass, EDIF and
  VHDL)
• General netlist (SPICE)
• Schematic
• Process Technologies
• Full Custom CMOS 5, 3, 1.2, 1.0, 0.8, 0.6, 0.5,
  0.35 micron
• (Standard Cell) Bi-CMOS 0.8 Micron
• Semi Custom ASIC CMOS 5, 3, 0.8 micron
• (Gate Array) Bipolar Transistor Array

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ASIC Design Details contd..

• Design
• Partitioning
• Functional and Logic Design using VHDL or Gate
  Level
• Logic and timing simulation
• Circuit design and simulation
• Test vector generation and evaluation
• Layout
• Floor planning
• Geometric device design
• Design rule checks
• Circuit and logic verification

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ASIC Design Flow using Mentor
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SOC Design Flow
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Mentor Graphics EDA Suite

• EDA Solutions for FPGA/PLDs
• FPGA Advantage Integrated Design Environment
  for High Complexity FPGA device design.
• HDL Designer Complete Design and Management
  Solution for FPGA/PLD designs
• ModelSim Simulation, Advanced Verification and
  Debugging
• Leonardo Spectrum Synthesis environment to
  create PLDs, FPGAs and ASICs in VHDL or Verilog.
• Precision Physical Synthesis Integrated RTL and
  physical FPGA synthesis solution that addresses
  the productivity and timing closure challenges

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Mentor Graphics EDA Suite

• EDA Solutions for IC Design Verification
  (ASICS)
• Design Architect-IC Schematic capture,
  netlisting, simulation setup and results viewing,
  all integrated within the Mentor Graphics
  analog/mixed-signal SoC design flow.
• Accusim ADMS Simulation Functional
  verification.
• IC Station-SDL It includes all of the
  functionality to create IC layouts based on
  information from a logic source, for digital and
  analog layout design.
• DRC LVS Design Rule Checker Layout vs
  Schematic used for Physical Verification of the
  Layout for manufacturability. Also used for
  Parasitic Extraction.
• Mach TA ADMS Used for Post Layout-Simulation

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Mentors Design Architect Environment
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Mentors IC Station Environment
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ASIC Layout
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Questions

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