Edge D FF

1
Edge D FF
module edgeDFF(d,q,qb,clk) input d,clk output
q,qb wire r,s,a,b nand 2 setL1(a,b,s) nand
2 setL2(s,a,clk) nand 3 resetL1(r,s,clk,b) n
and 2 resetL2(b,r,d) nand 2
outputL1(q,s,qb) nand 2 outputL2(qb,r,q) init
ial monitor("at ",stime," clk ",clk,", d
", d,", s ",s,", r ",r,", q ",q,", qb
",qb) endmodule
2
Edge D FF, tester
module test reg clk,d wire q,qb edgeDFF
dut(d,q,qb,clk) initial begin clk 0 d
0 140 d 1 20 d0 20 d1 160 d
0 200 finish end always 50 clk
clk endmodule
3
Edge D FF, test log
at 0 clk 0, d 0, s x, r x, q x,
qb x at 2 clk 0, d 0, s 1, r x,
q x, qb x at 3 clk 0, d 0, s 1,
r 1, q x, qb x at 50 clk 1, d 0,
s 1, r 1, q x, qb x at 53 clk 1,
d 0, s 1, r 0, q x, qb x at 403
clk 0, d 0, s 1, r 1, q 0, qb 1 at
450 clk 1, d 0, s 1, r 1, q 0, qb 1 at
453 clk 1, d 0, s 1, r 0, q 0, qb
1 at 500 clk 0, d 0, s 1, r 0, q
0, qb 1 at 503 clk 0, d 0, s 1, r
1, q 0, qb 1
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81 Mux
module mux(signalsin, choice, signalout) input
07 signalsin input 02 choice output
signalout assign signalout (choice
3'd0) ? signalsin0 (choice 3'd1) ?
signalsin1 (choice 3'd2) ? signalsin2
(choice 3'd3) ? signalsin3 (choice
3'd4) ? signalsin4 (choice 3'd5) ?
signalsin5 (choice 3'd6) ? signalsin6
(choice 3'd7) ? signalsin7
1'bz endmodule
5
81 Mux, tester
module testmult reg clk, load reg 310 a,
b wire 630 ab mult multi(clk, load, a, b,
ab, done) initial begin load 0 clk
0 a 30 b 7 200 load 1 100 load
0 3200 finish end always 50 clk
clk always _at_(posedge clk) strobe("ab d, done
b",ab, done) endmodule
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81 Mux, test log
Compiling source file serial multiplier
module Compiling source file serial multiplier
test ab x, done 0 ab
x, done 0 ab 7, done
0 ab 64424509443, done 0 ab
96636764161, done 0 ab 112742891520, done
0 ab 840, done 0 ab
420, done 0 ab 210, done
1 Exiting VeriWell for Macintosh at time 3500 0
Errors, 0 Warnings, Memory Used 45004
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Priority Encoder Basic Element
module priorityelement(request, grantin, accept,
grantout) input request, grantin output
accept, grantout assign accept request
grantin assign grantout !request
grantin endmodule
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Priority Encoder Chain
module prioritychain(requests, accepts,
taken) input 07 requests output 07
accepts output taken wire 07
grantout priorityelement pe00(requests0,1'b1,
accepts0,grantout0) priori
tyelement pe01(requests1,grantout0,
accepts1,grantout1) priorityeleme
nt pe07(requests7,grantout6,
accepts7,grantout7) assign taken
!grantout7 endmodule
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Priority Encoder Encoder
module encoder(onehots,code) input 07
onehots output 02 code assign code
onehots0 ? 3'd0 onehots1 ? 3'd1
onehots6 ? 3'd6 onehots7 ? 3'd7
3'd0 endmodule
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Priority Encoder Complete
module priorityencoder(requests, taken,
code) input 07 requests output
taken output 02 code wire 07
accepts prioritychain pc(requests, accepts,
taken) encoder en(accepts, code) endmodule
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Priority Encoder Test
module test reg 07 requests wire 02
code wire taken priorityencoder dut(requests,
taken, code) initial begin 100 requests
8'b00000000 100 strobe("requests
b",requests," taken ",
taken," code ",code) 100 requests
8'b00000001 100 strobe("requests
b",requests," taken ",
taken," code ",code) 100
finish end endmodule
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Serial Multiplier
module mult(clk, load, ain, bin, eb,
done) input clk, load // clock and load/start
signal input 310 ain, bin // multiplier and
multiplicand of n bits output 630 eb //
product of 2n bits output done // product-ready
signal reg 310 a // hold copy of
multiplicand reg 630 eb // hold multiplier
and product reg done // multiplication done and
result ready signal reg 50 i //
multiplication loop counter initial begin done
0 i 0 end // startup with
done false and loop counter zero wire 320 s
eb6332 ((eb0) ? a 32'd0)
// 's' always holds the sum of the accum
product // the low order multiplier
times the multiplicand
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Serial Multiplier
always _at_(posedge clk) begin // it's a clocked
system if (load (i0)) begin // start a mult
on load, if idle, (i0) done lt 0 // not done
yet a lt ain // load the multiplicand eb633
2 lt 0// zero the accumulated
product eb310 lt bin// load the
multiplier i lt 32 // set the loop
counter end if (i!0) begin // if
multiplicant in progress eb630 lt s,
eb311 //
combined update of accum prod shift of mult i
lt i-1 // decr loop count if (i1) done lt
1// are we done yet? end end endmodule
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Stack
module stack(reset, push, pop, top, datain,
dataout) input reset, push, pop, top input
30 datain output 30 dataout reg 031
stk07 wire 30 dataout integer
tos always _at_(posedge reset) tos lt 0 always
_at_(posedge push) begin stktos
lt datain tos lt tos 1 end always _at_(posedge
pop) tos lt tos - 1 assign dataout (pop)
? stktos (top) ? stktos-1 4'bz endmodule
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Stack
module test define setdata 50 data
4'b define push 50 push 1 define pop
50 pop 1 define top 50 top 1 define
noop 50 push 0 pop 0 top 0 reg
reset,push,pop,top reg 03 data wire 03
dataout stack stacki(reset, push, pop, top,
data, dataout)
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Stack
initial begin reset 1 100 reset 0 100
noop setdata 0001 push strobe("push
",data)noop top strobe("top
",dataout)noop setdata 0010 push
strobe("push ",data)noop setdata 0011
push strobe("push ",data)noop top
strobe("top ",dataout)noop pop
strobe("pop ",dataout)noop top
strobe("top ",dataout)noop pop
strobe("pop ",dataout)noop pop
strobe("pop ",dataout)noop end
endmodule
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isRISC Defines
define op_add 8'd0 define op_sub 8'd1 define
op_beq 8'd2 define op_loadlit 8'd3 define
op_stop 8'd4 define reg0 4'd0 define reg1
4'd1 define reg2 4'd2 define reg15 4'd15
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isRISC Memory
module mem(clk, memWrite, mar, memData) input
clk input memWrite / write to memory?
/ input 310 mar / address for R/W
/ inout 310 memData/ bus for R/W data
/ reg 310 memArray 01023/ memory
array / integer i
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isRISC Memory
/ if write requested, do so / always
_at_(negedge clk) if (memWrite)
memArraymar lt memData / if not write
requested, do a read whether requested or not
/ assign memData (memWrite) ? 32'bz
memArraymar / place a program in memory,
starting at address zero / initial
begin memArray0 op_loadlit, reg0,
20'd4 memArray1 op_add, reg1, reg0,
reg0, 12'd0 memArray2 op_stop,
24'd0 for (i 3 ilt1023 ii1) memArrayi
32'b0 end endmodule
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isRISC Data Path
module dp(clk, regRwrite, regAaddr, regBaddr,
regRaddr, aluW, aluE, aluCin,cc, dpDataIn,
result) input clk input regRwrite / write
to result reg? / input aluW, aluE, aluCin /
alu controls / input 30 regAaddr, regBaddr,
regRaddr / addresses of
A, B, and R regs / output 10 cc /
condition codes from current op / input 310
dpDataIn / input word to dp / output 310
result / output word from dp / reg 310
regs015 / register array / wire 310 x
regsregAaddr / x input to alu (reg A)
/ wire 310 y regsregBaddr / y input to
alu (reg B) / wire 310 tc01 / "TC01"
logic / (aluE) ? ((aluW) ? !y y) ((aluW) ?
32'd-1 32'd0) wire 310 result x tc01
aluCin / the adder gives
x tc01(y) Cin /
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isRISC Data Path
always _at_(negedge clk) if (regRwrite)
regsregRaddr lt dpDataIn / if
write-to-R, do so on Negative Edge of clock
/ assign cc result 32'd0,
result31 / current
condition codes / / debugging stuff / always
_at_(negedge clk) if (regRwrite)
strobe("writing register d with d", regRaddr,
result) /always _at_(posedge clk)
strobe("writing r1 d", regs1)/ endmodule
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isRISC Controller
module cntl(reset, clk, opcode,cc, cntlBrInBasep,
aluToDP, pcToDP, litToDP, latchPC, cntlNSI,
latchIR, latchBASE,memWrite, latchMAR,
sourceMDR, latchMDR, readCode,regRwrite, aluW,
aluE, aluCin) input reset, clk input 70
opcode input 10 cc output
cntlBrInBasep output aluToDP / pass the alu
result / output pcToDP / pass the PC to the
dp input / output litToDP / pass the current
IR.literal to dp input / output latchPC /
latch the PC / output cntlNSI output latchIR
output latchBASE / latch the BASE / output
memWrite / do a memory write / output
latchMAR output sourceMDR output
latchMDR / latch the MDR / output
readCode output regRwrite output aluW, aluE,
aluCin
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isRISC Controller
reg run / machine is running?, or stopped?
/ reg 10 scc / saved cc (for next branch)
/ reg cntlNSI / is next inst. is NSI or branch
/ integer state / controller state /
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isRISC Controller
always _at_(posedge clk) if (reset) begin state
lt 1 cntlNSI lt 1 run lt 1 end else if (run)
case (state) / main cntl state case / 0 /
advance the PC / begin state lt
1 cntlNSI lt 1
/ assume the next is not
a branch / end 1 / MAR PC / state
lt 2 2 / MDR MEMMAR a.k.a. PC
/ state lt 3 3 / IR MDR (a.k.a.
MEMPC) /
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isRISC Controller
4 / decode instruction / case (opcode)
op_add state lt 10 op_sub state lt
20 op_beq state lt 30 op_loadlit state
lt 40 op_stop state lt 50 endcase
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isRISC Controller
always _at_(posedge clk) strobe("state d",
state) assign latchPC (state0) assign
latchMAR (state1) assign readCode
(state1) assign sourceMDR
(state2) assign latchMDR
(state2) assign latchIR
(state3) assign aluW (state20) assign
aluE (state10) (state20) assign
aluCin (state20) assign aluToDP
(state10) (state20) assign litToDP
(state40) assign pcToDP 0 assign
latchBASE 0 assign memWrite 0 assign
regRwrite (state10) (state20)
(state40)
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isRISC Top (defns)
module top(reset, clk) dataIn,
dataInValid, dataOut, dataOutValid) input
reset, clk input 310 dataIn input
dataInValid output 310 dataOut output
dataOutValid / GLUE REGISTERS / reg 310
PC, / program counter (starts at zero)
/ IR, / instruction register / MAR, /
memory address register / MDR, / memory data
register / BASE / base register for short
range branches /
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isRISC Top (defns)
/ INSTRUCTION FORMAT / wire 70 opcode
IR3124 wire 30 regAaddr
IR1916 wire 30 regBaddr
IR1512 wire 30 regRaddr
IR2320 wire 190 literal IR190 /
MEMORY / wire memWrite
/ request write at current address / wire
310 memData/ word bus to/from memory
/ mem memi(clk, memWrite, MAR, memData)
/ instantiate the mem module /
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isRISC Top (Cntl)
/ CONTROLLER / wire 10 cc / current
condition codes / wire aluToDP, pcToDP,
litToDP / which source to give to DP?
aluResult?, PC, literal, or memory (default)
/ wire latchPC / latch the PC? / wire
cntlNSI / next inst is NSI? / wire
latchIR / latch the IR? / wire latchMAR /
latch the MAR? / wire latchMDR / latch the
MDR? / wire regRwrite / write to the result
register? / wire aluW, aluE, aluCin / alu
controls / wire cntlBrInBase / do a branch on
the current BASE? / wire readCode / read
code? (or data?) / cntl cntli(reset, clk, /
instantiate the controller / opcode, cc,
cntlBrInBasep, aluToDP, pcToDP, litToDP,
latchPC, cntlNSI, latchIR, latchBASE, memWrit
e, latchMAR, sourceMDR, latchMDR,
readCode, regRwrite, aluW, aluE, aluCin)
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isRISC Top (Cntl)
/ CONTROLLER / wire 10 cc / current
condition codes / wire aluToDP, pcToDP,
litToDP / which source to give to DP?
aluResult?, PC, literal, or memory (default)
/ wire latchPC / latch the PC? / wire
cntlNSI / next inst is NSI? / wire
latchIR / latch the IR? / wire latchMAR /
latch the MAR? / wire latchMDR / latch the
MDR? / wire regRwrite / write to the result
register? / wire aluW, aluE, aluCin/ alu
controls / wire cntlBrInBase/ do a branch on
the current BASE? / wire readCode / read
code? (or data?) /
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isRISC Top (Datapath)
/ DATAPATH / wire 310 dpDataIn,
dpDataOut / paths to/from dp / dp dpi(clk,
regRwrite, regAaddr, / instantiate the datapath
/ regBaddr, regRaddr, aluW, aluE, aluCin,
cc, dpDataIn, dpDataOut) assign dpDataIn
/ select the input to the datapath /
(aluToDP) ? dpDataOut /current output of
datapath? / (pcToDP) ? PC /PC? /
(litToDP) ? 12'd0, literal /literal? /
memData /or a word from memory? /
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isRISC Top (Active Regs)
/ GLUE REGISTER ACTIVITIES / always _at_(negedge
clk) / MAR / if (latchMAR) MAR lt (readCode)
? PC dpDataOut / latch the PC or the
datapath output / always _at_(negedge clk) / MDR
/ if (latchMDR) / from mem or dp / MDR
lt (sourceMDR) ? memData dpDataOut /
latch a word from mem or datapath output
/ always _at_(negedge clk) / IR / if (reset)
IR lt 0 else if (latchIR) IR lt memData
/ latch an instruction from memory /
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isRISC Top (Active Regs)
always _at_(negedge clk) / PC / if (reset) PC lt
0 else if (latchPC) PC lt (cntlNSI) ? (PC
1) (BASE literal) / latch PC1 or the
current short-branch address / always _at_(negedge
clk) / BASE / if (reset) BASE lt 0 else if
(latchBASE) BASE lt dpDataOut / change the
base to the current datapath output / always
_at_(posedge clk) strobe("MAR d, MDR d, PC d,
IR d",MAR,MDR,PC,IR) endmodule