Competence of the Computer Architecture Group

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Interconnection NetworksandScalable Crossbars
Prof. U. Brüning Computer Architecture
Group Institute of Computer Engineering University
of Mannheim ulrich_at_ti.uni-mannheim.de
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Overview

• Future_DAQ workpackages
• Embedded optical transceiver cell
• Cascadable 32x32 crossbar switch
• Interconnection Networks
• First Results
• OASE
• SWORDFISH
• Scalable Crossbar

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ATOLL

• ATOLL Chip
• Network on a Chip
• die size 5.7 x 5.7 mm
• 4.5 Mio. Transistors
• UMC 0.18µm CMOS
• 6 clock domains 250MHz main areas133MHz PCI-X
• 64bit architecture

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OASE

• OASE Chip
• SERDES and Optical Transceiver on a Chip
• die size 2.4 x 5.0 mm
• UMC 0.18µm CMOS
• 2,5GHz bidirectional data rate
• 125MHz parallel interface with DDR LVDS
• VCSEL with direct flip chip mounting

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OASE

• OASE Optical Attachment
• VCSEL with direct flip chip mounting
• Bottom emitter VCSEL
• Fiber mounting with self-alignment structure
• SU-8 on glass
• Alignment of GaAs wafer to glass substrate at
  wafer level
• Very low cost

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SWORDFISH

• IN Simulator
• Very flexible
• parametrizable
• Wormhole and packet routing
• Topology generator
• MPI like traffic pattern generation
• Plug ins for routing, arbitration
• Execution driven simulation for large INs

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Scalable Crossbar

• Parameter
• Number of Ports
• Data width
• debug port

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Scalable Crossbar

• Functional View
• Structured in
• Inport
• Outport
• debug port
• interconnect matrix
• FIFOs for reverse flow control

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Scalable Crossbar
InPort
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Scalable Crossbar
OutPort
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Scalable Crossbar

• Crossbar Generation
• PERL script
• Generates the RTL description of a NxN Crossbar
• Number of Ports, word width, FIFO depth, cycle
  time,
• Verilog source code
• constraint file
• synthesis control file
• reports
• test bench generation with assertions

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Scalable Crossbar
Timing Results
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Scalable Crossbar
Area for Standard Cells

• 32 x 32 Crossbar feasible but with cycle time
  below 200MHz
• Take care of pin limitation

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Results

• OASE
• TX tested and only one small modification in the
  high speed analog part required
• Input Jitter of 100ps at LVDS clock can be
  accepted due to PLL filtering
• RX could not be tested completely due to analog
  simulation fault (VCO in CDR to slow)
• Network Simulator
• fully functional
• Swordfish C modular simulator with plug ins
• Scalable Crossbar
• Automatic generation of parametrized Crossbar
• Verified by simulation (hardware structure from
  ATOLL)

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Thank you for your kind attention!Questions?
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Present Work

• Prototype Testbed
• Based on Virtex4 V60
• Test of MGTs and OASE
• Jitter measurements
• Nearest neighbor interconnect test
• Test of fast host interfaces (HTX)