A Small Vera/Verilog Example

1
A Small Vera/Verilog Example
Compilation Sequence

• 1 is filename (w/o .v) and
• top module name

!/bin/sh template vera -tem -t 1 -c clock
1.v compile vera -cmp -vlog 1.vr vcs vcs
-vera v2k 1.v 1_shell.v 1.test_top.v sim ./s
imv vera_load1.vro vera -cov_text_report
1_test.db cat 1_test.txt
2
Simple Verilog Design
module b01 (line1, line2, reset, out, overflow,
clock) input line1, line2, reset, clock wire
line1, line2, reset, clock output out,
overflow reg out, overflow integer st0

• A simple state machine in Verilog

3
Interface File (b01.if.vrh)
interface b01 output line1 OUTPUT_EDGE
OUTPUT_SKEW output line2 OUTPUT_EDGE
OUTPUT_SKEW output reset OUTPUT_EDGE
OUTPUT_SKEW input out INPUT_EDGE
input overflow INPUT_EDGE input clock
CLOCK // end of interface b01

• Skew indicates application time relative to clock
  edge
• ?_EDGE indicates hold or pulse
• Notice that CLOCK is an input

4
Coverage Results

• Create a .txt coverage report from the .db file

vera -cov_text_report 1_test.db cat 1_test.txt
Automatically Generated States Bin
hits at least

s_0
45 1 s_1
53 1


5
A Vera Testbench, Part 1
class RandomInputs rand reg10 line1,
line2 coverage_group cv()
sample_event _at_(posedge CLOCK) sample
b01.out

• A class to generate input data
• Coverage group with automatic state bins

6
A Vera Testbench, Part 2
program b01_test integer i
RandomInputs rnew _at_(posedge CLOCK)
b01.reset 1 _at_(posedge CLOCK)
b01.reset 0 for(i0 ilt100 i)
_at_(posedge CLOCK) void r.randomize()
b01.line1 r.line1 b01.line2 r.line2
// end of program b01_test