Hardware implementation of an MPEG1 Layer1 audio encoder

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Hardware implementation of an MPEG-1 Layer-1
audio encoder
EE4 Final Year project 2000-2001

• Sami Khawam

S.Khawam_at_ug.ee.ed.ac.uk
Friday, January 26, 2001
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Presentation Outline

• 1. Aims of the project
• 2. Overview of MPEG algorithm
• 3. Implementation
• 4. Project organisation
• 5. Further extensions and modifications

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1. Aims of the project
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Aims of the project

• Hardware core for MPEG-1, layer-1 (MP1) audio
  encoding.
• Description in Verilog-RTL for flexibility.
• Synthetisable to FPGA architecture.

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Advantage
Commercial IP cores and chips exist, but are
mainly based on software and DSP cores. The
advantages in hardware

• High speed, thus real-time possibility.
• Lower power consumption.
• Low cost by using low cost FPGAs.

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Applications

• Portable or standalone audio record and playback
  devices.
• Voice-over-IP systems.
• Standalone internet-radio servers.

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2. Overview of MPEG algorithm
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Encoding System
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Analysis Filterbank

• Time to frequency domain conversion.
• Critically sampled 384 inputs, 384 outputs.
• 32 equal width subbands.
• Like parallel band-pass.
• Equation from ISO document
• Can be optimised

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Psychoacoustic Model

• Key to maintain signal quality at high
  compression ratios.
• Based on absolute hearing threshold
• and the frequency masking properties of the ear.
• Finds the Signal-to-Mask Ratio value for each
  subband.

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SMR calculation outline

• 512-point FFT and window then squaring to get
  power.
• Identify tonal (sine like, local peaks) and
  non-tonal (noise like) maskers.
• Remove the ones that are blow the threshold of
  hearing.
• Remove weak tonal maskers too close to strong
  maskers.
• Find global masking threshold absolute
  threshold contribution from maskers.
• Find minimum masking threshold in each subband
  (from individual masking threshold and GMT).
• SMR of each subband MMT - Peak power of subband.

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Bit allocation and Quantisation

• Find the minimum number of quantisation bits to
  make the quantisation noise inaudible.
• Uses iteration to find the minimum difference
  between SMR and SNR.
• Attempts to get the desired final bit rate.
• Then linearly quantise the subband samples.

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Bitstream formatting

• Header
• For each of the 32 subbands
• number of bit allocated
• scale factor
• quantised samples
• Optional CRC error check.

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3. Implementation
FPGA
PC
384 PCM frame
RS232
MPEG
RS232
driver
Encoder
Encoded data

• Audio encoded frame by frame
• PC sends PCM audio and receives the encoded data.
• Encoded data saved in .mp1 format by the PC.

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4. Project Timeline
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Second Term

• Build the 3 main components separately then
  integrate them.
• For each component
• Design the hardware based on C and Matlab source.
• Write adequate test-benches for simulation.

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Third Term

• Implement the integrated blocks and RS232
  transfers on the FPGA.
• Write C program for transferring data between the
  PC and the board.
• Create test samples.
• Write documentation.

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5. Further extensions and modifications
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Problematic issues

• FPGA too small.
• Low memory availability of the FPGA external
  DRAM needed.
• Psychoacoustic model too design-time expensive.

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Possible solutions

• Lower complexity psychoacoustic model. e.g. using
  FFTs find the average sound power level for each
  subband and treat result as SMR.
• Computation of standard functions on the PC, e.g.
  FFT in order to save memory and design time.

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Further extension

• Support for layer 2.
• Implementation of decoder.
• Optimisation (speed and size) of single
  components, e.g. like the filterbank.