Introduction to IC Test Technology

1
Introduction to IC Test Technology

• H. T. Vierhaus
• Brandenburg University of Technology Cottbus
• Computer Engineering Group

2
Outline
1. What is Test ?
2. Test for Integrated Circuits
3. IC Production Test Challenges and Bottlenecks
4. Development of Computer-Aided Test
5. New Challenges beyond Production Test
6. The Future of Test Technology
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1. What is Test ??
System (Hardware, Software, Mechanical,
Electrical)
Output signals
Input signals
If there is a fault or defect, make it apparent !
Weak Points

• The quality of test always depends on the
  selection of test cases.

• A test procedure can hardly be exhaustive with
  respect to possible
• fault cases / fault conditions for complex
  systems.

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Validation
System Model (Hardware, Software, mechanical,
electrical)
Input signals
Output signals
Validate the correctness of a system model at one
or at various levels of abstraction !
Mostly done by means of simulation.
Weak Points

• The quality always depends on the selection of
  test cases,

• A simulation can hardly be exhaustive with
  respect to possible
• input conditions and internal conditions for
  complex systems.

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Formal Verification
System Model 1
System Model 2
Prove that Model 2 is equivalent to Model 1
Strong Points

• Can prove correctness of a design in a
  mathematical sense !

Weak Points

• Needs a correct standard.
• Limited applicability to specific models.
• Never applicable to real-life hardware.

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What Can / Must be Tested
Software
Hardware
Prototypes
HW / SW - Systems
Units after production
Systems and devices in the field of application
Mechanical / electrical / optical systems
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A Universe of Faults
Faults Errors
in operation
System
Design
all
Hardware
Implem.
in oper.
implementat.
Faults
Handling errors
System
Manufacturing
specification
HW / SW
-
defects
design
Stress
aging
hidden
Single event
(voltage, heat)
prod. defects
upsets (SEUs)
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2. Test for Integrated Circuits
IC test problems are as old as IC test
technology. Typically test technology has
been lagging production and even
design technologies by 5-10 years.
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Defects, Faults, Failures
Radiation, EM-coupling
may cause a failure
may cause an error
may cause a fault
Defect
Fault
Failure
Error
in computers
permanent
inter- mittent
effective overwritten latent
transient
static
dynamic
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Limitations of Production Testing
Radiation, EM-coupling
may cause an error
may cause a fault
Defect
Fault
Failure
Error
in computers
permanent
inter- mittent
effective overwritten latent
transient
static
dynamic
Testable by production test
11
On-Line Testing
Radiation, EM-coupling
may cause a fault
Defect
Fault
Failure
On-Line Testing
Error
Error Correction
in computers
permanent
inter- mittent
effective overwritten latent
transient
static
dynamic
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3. IC Production Test
Safety-critical applications (avionics,
automotive) require defect rates below one part
per million.
Even zero parts per million is becoming common
in automotive applications.
Design validation, verification and test are
becoming the bottlenecks in IC and system design
and manufacturing !
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IC Test Technology-Overview
Wafer Test
Chip Test
Packaging
(device test)
IC Production
Wafer test by manufacturer
chip (die)
Device test mainly packaging / assembly house
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Wafer Test
is performed on the full wafer before
slicing using test-access via bundles of needles.
Parametric Test Specific test structures, e.
g.on scribe lines
or via chip-pads
Functional Test By chip-wize test access
Behavioral test under normal operation
Structure-oriented test in a specific test mode
(also including built-in self test)
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Production Testing
Off-line Test Generation Process
Test System Control
Test Generator
Power Supply
Test Analyzer
test data
Off-line Test Program Generation
DUT-Board
test program
DUT
Test Adaptor
Problems Test equipment cost rises strongly with
test speed and pin count ! Test
costs per die depend on test time.
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Test Challenges
Test equipment cost
Ever -increasing complexity of chips under test
Limited test access to internal circuit nodes for
control and observation
More complex fault behavior of ICs in
advanced technologies, rising share of dynamic
versus static faults
Test coverage of real operating conditions
Test yielding functionally irrelevant faults and
yield loss
Test misses............
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Behavioral Test
Device under Test (DUT)
n inputs
k outputs
(black box)
For a combinational circuits of n inputs, the
number of test patterns is z 2n . Assuming a
sequential depth of m, the number z 2 (nm).
Real life n 100, m 10
Test may last hours to weeks !
Exhaustive testing is impossible !!
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Many Problems
Production test is a cost problem and a
complexity problem.
A test that covers all possible functional states
and conditions is impossible.
Without design for testability IC test becomes
impossible.
The quality of a test process critically depends
on the quality of the design for test strategy.

A test approach which is non-exhaustive may miss
conditions and states that fault-relevant.
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Migration from External Test to BIST
Parametric tests
Test System Control
Core
Test Generator
Power Supply
Test Analyzer
DUT-Board
Test Contr.
Test Analy- sis
Test Gene- ration
Chip
migration
Test Adaptor
Start self test
Test results
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4. Development of Computer-Aided Test
System Level Design
Specification (e. g in SystemC)
RT-Level Design
Looks nice, but does not work! Even
silicon compilers failed !
RT-level netlist
Logic Design
Gate level netlist
Physical Design
Layout
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Back Annotation
System Level Design
VHDL, Verilog
Specification (e. g in SystemC)
RT-Level Simulation, verification
RT-Level Design
RT-level netlist
Logic Simulation, Verification
Logic Design
Gate level netlist
Extraction, Circuit simulation
Physical Design
Layout
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Testability Analysis
System Level Design
VHDL, Verilog
Specification (e. g in SystemC)
RT-Level Simulation, verification
RT-Level Design
Test Guru
RT-level netlist
Logic Simulation, Verification
Logic Design
takes a look
Gate level netlist
Extraction, Circuit simulation
Physical Design
Layout
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Testability Analysis (2)
System Level Design
VHDL, Verilog
Specification (e. g in SystemC)
RT-Level Simulation, verification
RT-Level Design
Rule Base
RT-level netlist
Logic Simulation, Verification
Logic Design
takes a look
Testability Analysis
Gate level netlist
Extraction, Circuit simulation
Physical Design
user information
Layout
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Logic Structures
Combinational logic
D
cl
D
cl

D
cl
gt 1
gt 1

D
cl
D
cl

D

cl
gt 1
D
D

gt 1
cl
cl
D
cl
Flip-Flops
D
cl
Flip-Flops
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Testability Rules
Combinational logic
D
cl
D
cl

1

D
cl

gt 1
D
gt 1

D
cl
3

D

cl
gt 1
D
D

gt 1
cl
D
cl
2
D
cl
Avoid logic redundancy
1
No feedback in combinational logic
2
No mixing of clock and signal inputs
3
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Structure-Oriented Test
VDD
Stuck-at-1

gt 1
gt 1

modeled faults


gt 1

gt 1
Stuck-at-0
GND
Based on information on the internal structure of
a circuit assumptions are made about specific
types of faults (fault models). Then the test
process is tailored to find such specific faults
if they are there in the circuit.
Significant reduction of test complexity versus
black box test
Automatic generation of optimized pattern sets
(test patterns)
The fault model must somehow describe the real
fault behavior of the circuit !
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Fault Models
Static fault models
Single circuit node stuck-at- 0 or stuck-at-1
(ssa-model)
standard fault model
Eldred, 1959
Multiple stuck-at-faults
(scarcely used in the 1980s / 90s)
Dynamic fault models
Gate-delay-fault a single gate switches too
slowly
Path-delay-fault a spcific logic path is
switched too slowly
Transistion fault model a specific gate cannot
perform a specific transition
Switch-Level fault models
Transistor stuck-on / off A specific
transistor is always on / off
Line- bridge / line break A line (wire) has a
short (with an other signal)
or an interrupt
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Problems with Fault Models
The stuck-at-model was quite useful for bipolar
circuits but proved to be too crude for CMOS
circuits.
Dynamic properties of CMOS circuits made test
based on dynamic fault models a necessity.
More test patterns required !
Fault models must match the available decription
of the circuit !

Tends to behave like a node stuck-at 0 / 1 for
bipolar circuits (GND dominating logic
strenght) but not for CMOS !


line-bridge
gt 1

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Bridge-Type Faults
VDD
Fault effect
resistive bridge
Logic network
Reduced voltage levels
0
Uncertain evaluation (Byzantine generals problem)
1
GND
voltage
VDD
VDD
Logic 1
1
uncertain
0
Raised 0-level
Logic 0
GND
GND
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Overcurrent Test
VDD
Pros
Can detect fault beyond stuck-at, specifically
bridge- type or on-type fauls.
resistive bridge
Logic network
0
Current measurement gives new points of
observability
1
Short input test sets
GND
Cons
VDD
Works only if fault-currents dominate normal
leakage currents
Needs specific units for current
measurement (IDDQ-monitors)
1
0
Raised 0-level
IDDQ monitors are complex and eat up voltage
swing.
Parasitic current flow (IDDQ) under fault
conditions
IDDQ monitor
GND
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Test Pattern Generation
(Roth, 1967)
VDD

1
gt 1
gt 1

Set inputs for fault propagation
Observable outputs

0

gt 1
Set inputs for fault exitation

gt 1
Stuck-at-0
GND
Define fault location
Find path to primary output(s)
Find input settings for fault excitation and
propagation
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Test Access to Sequential Circuits
VDD
FF

FF
1
gt 1
FF
gt 1

FF
FF

FF
0

gt 1
FF

gt 1
FF
FF
Stuck-at-0
GND
feedback loop
Test access is significantly reduced !
FFs must be initialized
Multiple patterns to be applied for single fault
detection
Faults may become self-masking
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Test for Sequential Circuit
fault
FF
FF
virtual ins
FF
virtual outs
FF
FF
FF
primary out
FF
FF
primary ins
Step 1 Excite fault condition
Step 2 Set path for propagation to primary output
Step 3 Justify side conditions for propagation
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Time Frame model
Faulty circuit
Faulty circuit
Faulty circuit
Faulty circuit
Faulty circuit
k clock cycles needed for fault propagation
m clock cycles needed for initialization
fault activation
The same circuit is multiplied (km) times. In
each time step, the necessary ATPG- actions are
performed (propagation, justifucation).
ATPG actions are done in time frames, whereby
ATPG tools can nandle only a few (typically 3)
time steps in combination.
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Sequential ATPG problems
The actual circut complexity is multiplied (e.
g. by 90 in sequ. ATPG benchmarks).
Multiple patterns need to be applied in a long
sequence even for a single fault.
A fault that affects its own propagation may
become self masking.
Sequential ATPG for real (large) circuits
explodes in complexity.
Known solution use strategies such as genetic
algorithms, which are difficult to optimize.
Sequential test for dynamic faults involves
specific timing models (fast- / slow clock).
Sequential ATPG is a must-to-avoid. It is in
limited use only for tests that require two
consecutive time steps in scan test technology.
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Test Pattern Volumes
Optimized Test for dynamic Faults (combinational)
Stuck-at Test (combinational)
IDDQ-Test
1
10
(for the same example circuit)
But IDDQ test is hardly used in nanometer
technologies, transient fault analysis
must do the job instead !
100
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Scan Path Structures
SC
SC
SC

Flip-Flops
gt 1
SC
gt 1

SC
cl
SC


gt 1
SC
SC

gt 1
cl
SC
Nomal in
SC
Scan out
S
out
Scan in
D
Scan Flip-Flops
Scan in
Scan control
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Scan Path History
First publications about 1975.
IBMs level sensitive scan design 1976
(Eichelberger, Williams).
Extension into (Built-in Self Test structures)
from 1979.
Compulsory in IBMs design from the late 1970s.
Wide industrial acceptance from about 1992.
Many suggestions to use larger basic elements, e.
g. for double latched scan to test dynamic
faults.
Multiple parallel scan path architectures
suggested around 1990 and in heavy industrial use
today.
Coupled with proper test generation technology,
also 2-pattern test for dynamic faults are
possible.
Problem Scan operation may cause high power
dissipation and high pulse
currents on VDD- and GND rails.
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Scan-Test Philosophy
Logic Cone
Logic Cone
Logic Cone
Logic Cone
Logic Cone
Scan out
Scan-in
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Independent Faults and X Inputs
Logic Cone
irrelevant inputs
Logic Cone
target fault
relevant inputs
Logic Cone
Test Strategy
Irrelevant inputs may have arbitrary logic
values !
Logic Cone
irrelevant inputs
Only relevant inputs must have deterministic
settings.
Logic Cone
Only 0.1 to 1 of inputs per test clock must be
set deterministically!
Scan out
Scan-in
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Test For Dynamic Faults
VDD
FF

FF
1
gt 1
FF
gt 1

FF
FF

FF
0

gt 1
FF
FF

gt 1
FF
FF
Stuck-at-0
GND
Initialisation Set inputs to define a logic path
including the gate / node
to be tested.
Test Change input(s) in order to
propagate the input /
output transition to an output.
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Built-in Self Test (BIST)
Test Gene- rator
Test Res- ponse Com- pactor

gt 1
gt 1



gt 1

gt 1
Start/ stop
GND
Signature out
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Multiple Input Scan Test
Device under (Scan-) Test
Test Input De-com- pactor / Decoder
Test Output Com- pactor / Encoder
Scan path
Logic
Scan path
Compacted / encoded test data
Scan path
Logic
Scan path
(up to 1000 parallel scan paths)
signature
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Deterministic BIST
Device under (Scan-) Test
Test Pattern Generator
Test Output Com- pactor / Encoder
Scan path
Logic
Scan path
Control
Scan path
Logic
Scan path
(up to 1000 parallel scan paths)
signature
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Current Problems in Production Test
High power dissipation during mass-transitions at
scan shift.
Dr. Pliva
Limited coverage of transient fault effects and
false faults by standard scan, since scan test
does not reproduce the real dynamic operating
conditions.
Fault diagnosis integrated into production test,
compatible with test response compaction.
Prof. Gössel
Test input data compaction to ratios between 100
and 1000.
Prof. Novak
Test coverage problems if the real logic is not
implemented as standard gates, but uses other
transistor-level circuits.
Prof. Straube
No systematic design for test for analog circuits
(???)
Dr. Mattes
No real solutions for asynchronous logic.
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5. New Challenges
Systems on a Chip (SoCs) consisting of
digital and analog and RF components plus complex
heterogeneous interconnects must be tested.
Scan test covers only part of the problem.
Worst Without the right soft- ware for embedded
processors, functional test becomes impossible !
D / A
Prof. Sonza-Reorda
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Hierarchical Self Test Concept

• External tester is replaced by internal test
  processor for non-time critical test control
  functions.
• BIST and/or embedded scan structures needed for
  production test are re-used for e. g.
  startup-tests.
• Structures available for on-line test are
  included in the test concept, e. g. parity
  control for bus structures.
• The test processor as the essential boot device
  needs special self-testing features.

MP-SoC with Test Processor
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Transient Faults and Single Event Upsets (SEUs)
Discharge of memory cells and circuit nodes
Charged particles

EM coupling

• Sources for transient faults
• Radiation
• EM coupling
• VDD- and GND-noise

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Contribution to Soft-Error Rates
Static combinational logic 11
Sequential elements (FFs, Latches) 49
Unprotected SRAM 40
Source S. Mitra, N. Seifert, M. Zhang, Q. Shi,
K. S. Kim, Robust System Design with Built-In
Soft Error Resilience IEEE Computer, Vol. 38,
No.2, Febr. 2005, pp. 43-52
Processors implemented in nano-technologies must
have on-line fault detection and compensation !
50
Hardware Test Technologies
Production Test
On-Line (Self-) Test
Built-in Self Repair (BISR)
Fault diagnosis
Error correction
Start-Up (Self) Test
At wafer-fab, off-line
In-field on-line
In-field, off-line
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7. The Future
Complex systems consist of hardware and masses of
software. Faults may occur on either side, often
almost impossible to distinguish.
Transient hardsware faults are becoming the rule,
not the exception. Compensation by hardware or
software becomes a must.
At least for long-time dependable systems, built-
in self repair (BISR) seems to become a necessity.
BISR does not work without embedded fine-grain
fault diagnosis.
System re-organisation and repair must even
work under additional transient fault effects.
Minimum extra power available for test,
diagnosis, repair !!