Design

1
Design Simulation of ADSL ATU-C Transport
Class 4 Transmitter

• By
• Team 5 for ELEN 603 at
• SCU

2
Objective

• Study the IEEE ANSI T1.413 Standards.
• Analyze the supplied Verilog and C code.
• Design the specification of the projects.
• Develop and verify the C and Verilog Code.
• Simulate individual modules Test Bench.
• Simulate, Analyze and Report the overall system
  Test Bench.

3
Input Data Channels

• AS0 Simplex Channel
• 1.536 MBPS
• DR 4884000 Ps
• Goes to Interleaved.
• LS0 C-Channel
• 16 KBPS
• DR 1284000
• Goes to Interleaved.

• LS1 Duplex Channel
• 160KBPS
• DR584000 PS
• Goes to Fast Data Buf.
• Embedded Operators Channel (EOC) is not supported.

4
Frames

• Fast Frame carries fast byte, 5 Bytes of LS1 and
  LEX Byte.
• Interleaved Frame carries AS0 and LS0.
• It requires Sync Byte, AEX and LEX bytes.
• Super Frames contains 68 frames.
• Last frame is the sync frame.
• 0,1, 34 and 35 are specially filled with CRC and
  IBS.

5
ADSL Transmitter Modules

• Delivers high rate digital data.
• Mux/Sync Module
• Framer
• Scrambler
• CRC
• FEC
• Interleaved

6
Mux/Sync Module

• Multiplexed different Channels
• Control flow of data through different modules
• Synchronized clocks through the sub modules

7
Scrambler and CRC

• Achieve d.c balance.
• Avoid long sequence of 0s and 1s.
• Checks Validity of data and redundancy.
• Use polynomials to scramble and add CRC bits.

8
FEC and Interleave

• Add redundancy Check Bytes according to message
  and check polynomials.
• Mix up various frames on the Interleave
• Interleave Depth should be 16.

9
Simulation Results

• Individual Test Benches.
• Verification and diagnostics.
• Integration piece by piece.
• Integrated Test Bench results.

10
Analysis Conclusion

• Used Synopsys VCS
• Short time led to some initial confusion
• Inconsistency of supplied code.
• Developed most code from Scratch
• Able to Simulate and Verify the behavior