Presentation Name 1

1
Digilent Spartan-IIE Board
www.digilentinc.com
2
XSV-1 Board from Xess Corp.
XCV50 - 699 XCV100 - 749 XCV300 -
899 XCV800 - 1599 To Order www.xess.com
3
Software for Labs

• V4.2i ISE Software
• Design Entry
• XST Synthesis
• Implementation
• Simulation (MXE-II)
• iMPACT Programmer
• CORE Generator
• Parameterizable Cores
• StateCAD/State Bencher
• State Machine Design
• HDL Bencher
• Test Bench Generation

4
Software for Students

• FREE ISE WebPACK
• Downloadable desktop solution
• HDL / ABEL synthesis simulation
• JTAG and 3rd party EDA support
• Supports all Xilinx CPLD families, Spartan II,
  next generation Spartan, and Virtex E/Virtex II
  (up to 300K gates)

• Xilinx Student Edition - v4.2i XSE
• Accepts VHDL, Verilog standard netlists
• Fitting and timing reports
• Supports all Xilinx CPLD families, Spartan II,
  next generation Spartan, and Virtex E/Virtex II
  (up to 300K gates)

5
Virtex-IIPlatform FPGA for Multiple Applications

• Density 40K to 8M gates
• Memory up to 3 Mbits
• Xcite Digitally Controlled Impedance
• On-Chip clock generation
• 16 Global Clocks
• Embedded High-Speed Multipliers

Processing Platform
DSP Platform
Connectivity Platform
Empower!TM Processing
XtremeDSPTM Solution
SystemIOTM Interfaces
6
Spartan-IIE
On-Chip Memory Distributed Memory Block
Memory External Memory
System Clock Management Digital Delay Lock Loops
(DLLs)
IOB
IOB
DLL
DLL
. . .
I O B
I O B
CLB
CLB
R A M
R A M
. . .
. . .
I O B
I O B
R A M
R A M
. . .
System Interfacing SelectI/OTM
Technology Support major I/O standards
Logic Routing Flexible logic implementation Vect
or Based Routing Internal 3-State bussing
CLB
CLB
DLL
IOB
IOB
DLL
7
CoolRunner-II
8
On-Chip Verification
ChipScope ILA System Diagram
Target FPGA with ILA cores
USER FUNCTION
USER FUNCTION
Chipscope ILA
PC running ChipScope
USER FUNCTION
Control
JTAG
JTAG Connection
MultiLINX Cable or Parallel Cable III
Target Board
9

• Advanced Teaching Tools

10
Computer Architecture
MicroBlaze Solution - MDK 2.1

• Soft Processor Core
• 32-bit - Harvard Bus RISC Architecture
• Size 900 Logic Cells
• Speed 125 MHz, 82 D-MIPS
• 32 General Purpose Registers 3 Operand
  Instruction Format
• IBM CoreConnnect Bus
• Standard Peripheral set
• Timer, Counter
• Arbiter
• UART, Interrupt controller, SPI
• GPIO, Watchdog timer
• External flash, SRAM interface

• GNU Development tools
• Demo Board from partners
• Sample applications

11
Digital Signal Processing