Basic Registers and Counters, VGA Timing

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Basic Registers and Counters, VGA Timing

• Anselmo Lastra

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First

• Lets talk about lab
• Best to use single clock for all FFs
• Make signals synchronous
• Note there are two uses for always
• To generate FFs
• Combinational only
• Latter does not turn regs into FFs
• Look at the synthesizer log

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Topics

• Office Hours
• After class
• Email me for time tomorrow
• Test details
• Basic registers and counters
• Enough for VGA lab
• CRT timing

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Test Covers

• Test will be open book, notes, and calculator
• No computer (no ModelSim, etc)
• Chapter 1
• Binary and hexadecimal numbers
• Binary addition, etc.
• Parity

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Chapter 2

• Boolean algebra
• Schematic diagrams
• Basic Simplification
• Karnaugh maps, up to 3 variables
• Making circuits from maps
• Gate types

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Chapter 3

• Basic circuit design
• Hierarchies
• Gate delays
• We deferred most of chapter

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Chapter 4

• Know what encoder, decoder, and mux are
• How to design them
• Logic
• Verilog
• Verilog styles (structural, dataflow, behavioral)
• Be able to write combinational Verilog programs

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Chapter 5

• Adders
• Complements
• Signed arithmetic
• How to express positive and negative numbers

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Definitions

• Register a set of flip-flops
• May include extensive logic to control state
  transition
• register also refers to fast memory for storing
  data in a computer
• Counter
• Register that goes through sequence of states as
  it is clocked
• Saw simple counter last week

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Simple Register

• Store D
• On posedge of Clock
• Clear signal normally high
• Power-up reset
• Symbol

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Clocking

• Typically dont want to load every clock
• Can gate the clock
• But skew problem

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Alternative

• If load H, then D is gated through
• Otherwise, Q is fed back
• Keep same value
• No clock gating

• Did this because D FF doesnt have no change
  behavior

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Counters

• Counter is a register has state
• Also goes through sequence of states counts
  on clock or other pulses
• Binary counter
• Counts through binary sequence
• n bit counter counts from 0 to 2n

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Ripple Counter

• Simple
• So Q will alternate H and L
• Why called ripple counter?

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Synchronous Counters

• Ripple counter is easy
• Asynchronous nature may cause problems
• Synchronous counter very common

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Synchronous Counter

• Does have sequence of gates
• What does it remind you of?

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Parallel Design

• Can gang these to make long serial-parallel
  counter

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Verilog Counter

• module count_4_r_v (CLK, RESET, EN, Q, CO)
• input CLK, RESET, EN
• output 30 Q
• output CO
• reg 30 Q
• assign CO (count 4'b1111 EN 1b1) ? 1
  0
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• Q lt 4'b0000
• else if (EN)
• Q lt Q 4'b0001
• end
• endmodule

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Lets Look at Video Timing

• Different set of slides

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What do you Need for VGA?

• Brainstorm
• Need Counter(s)?
• Is there any kind of state?
• Will you need a state machine?

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Today

• Expanded FFs to make registers
• Counters
• Ripple (cheap)
• Synchronous

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Next Time

• Test next
• Next week Cover registers/counters in more
  detail