FPGA Encrypt Decrypt Test

1
FPGA Encrypt / Decrypt Test
Ribbon cable
System clock
PLL
PLL
LVDS input
LVDS Output
Clock input
System clock
Lvds clock
Switching Matrix
Switching Matrix
Data input (16)
16 data output
const
16 lvds data pairs
tokout
lvds tokout
lvds tokin
tokin
Delay Module
testmode
Delay Module
sw
testmode
reset
sw
reset
LFSR
LFSR
FPGA1 Encryption mode
FPGA2 Decryption mode
2
FPGA Feedthrough Test 1
Pll locked
Deserializer
Serializer
System clock
LVDS input
LVDS Output
PLL
Lvds clock
Lvds clock
reg
reg
16 lvds data pairs
16 lvds data pairs
16 x 155Mbps
16 x 155Mbps
FPGA
BERT
2.5Gbps
2.5Gbps
3
FPGA Feedthrough Test 2
Pll locked
Deserializer
Serializer
System clock
Lvds clock
PLL
LVDS input
LVDS Output
Lvds clock
Switching Matrix
16 lvds data pairs
16 lvds data pairs
Delay Module
Test mode
16 x 155Mbps
16 x 155Mbps
LFSR
FPGA
BERT
2.5Gbps
2.5Gbps
4
Data Framing
Data stream
data
syn
data
syn
data
syn
255
Basic Architecture
Encrypt Matrix
Frame SYN
buf
Frame Align
buf
Decrypt Matrix
16 pair lvds data
token
token

• SYN inserted once every 256 words of data
• value of SYN determines presence of token