Bit Error Rate Transceiver

1
Bit Error Rate Transceiver

• Jordan C. Grosh
• and Samuel E. Moelius III
• jkgrosh,moelius_at_udel.edu
• (617 LUTs)

2
Linear Feedback Shift Register Interface
reg is an internal std_logic_vector(7 downto 0).
3
Linear Feedback Shift Register (cont.)

• On rising edge of clkin
• reg(7) lt reg(1) xor reg(2) xor reg(3) xor
  reg(7)
• reg(6) lt reg(0) xor reg(1) xor reg(2) xor
  reg(6)
• reg(5) lt reg(0) xor reg(2) xor reg(3) xor reg(5)
  xor reg(7)
• reg(4) lt reg(3) xor reg(4) xor reg(6) xor
  reg(7)
• reg(3) lt reg(2) xor reg(3) xor reg(5) xor
  reg(6)
• reg(2) lt reg(1) xor reg(2) xor reg(4) xor
  reg(5)
• reg(1) lt reg(0) xor reg(1) xor reg(3) xor
  reg(4)
• reg(0) lt reg(0) xor reg(1) xor reg(7)
• This is the result of iterating
• reg(7) lt reg(6) lt reg(5) lt reg(4) lt reg(3) lt
  reg(2)
• lt reg(1) lt reg(0) lt reg(1) xor reg(2) xor
  reg(3) xor reg(7)
• eight times.

4
BERT Interface
5
BERT Transmitter
a lt "010" dbusin lt 1024 ext_divlsb
set clock divisor
write lt 0
write lt 1
a lt "000" dbusin lt lfsr.dbusout
write lt 0
a lt 111
write lt 1
Yes
dbusout(2) 1?
a lt 001
null
No
lfsr.clkin is tied to int.
read is held low throughout.
6
BERT Receiver Synchronization
set clock divisor---same as in transmitter
count lt (1024 ext_divlsb) ? 8 - 1
count is an internal integer.
0
1
din
Yes
count 0?
count 0?
No
No
Yes
read is held low throughout. lfsr.dbusin
is 00000001 throughout.
count lt count - 1
a lt "001" lfsr.write lt 0 ready lt 0
lfsr.write lt 1
7
BERT Receiver Main Loop
Yes
dbusout(3) 1?
null
a lt 100
No
a lt 001
dbusout / lfsr.dbusout?
No
No
a lt 111
null
Yes
No
error / 15?
Yes
error lt error 1
lfsr.clkin is tied to int.
8
Achievements

• Critical path is 7.95 ns
• Peak (theoretical) operating frequency ? 125 MHz
• Latches are not always bad!
• A simple synchronization method
• Additional Features
• Ready signal
• Adjustable clock divisor

9
Tool Flow
Design / Coding

• Logical design.
• Initial coding.
• Revision and bug-fixes.

Pre-synthesis Simulation

• Testbench addresses
• Receiver and transmitter synchronize.
• Error-count remains stable at zero when no errors
  are introduced.
• Error-count increases when errors are introduced.

Synthesis

• Ensure that code is synthesizable.

Post-synthesis Simulation

• Ensure that synthesized code has same behavior
  under pre-synthesis testbench as pre-synthesis
  code.

On-board Testing

• Testing includes
• Receiver and transmitter synchronize when on
  separate boards.
• Error-count remains stable at zero initially
  after synchronization.
• Error-count saturates when connection is broken
  and then restored.