BitError Rate Tester BERT

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Bit-Error Rate TesterBERT
SCHEMATIC
Claudia BarreraG. Andres Mancera

• TA Mayra Sarmiento
• Professor Dr. Fouad Kiamilev

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DESIGN SUMMARY

• Number of flip-flops 341
• Number of latches 0
• LUT 1504
• CLB 376

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VERIFICATION METHODOLOGY
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VERIFICATION METHODOLOGY
We introduced a synchronization failure at the
RXBERT by changing its LFSR. This change allowed
us to verify the system was working properly.
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VERIFICATION METHODOLOGY
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BLOCK DIAGRAM - TXBERT
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BLOCK DIAGRAM - RXBERT
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I/O SIGNALS
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EXTRA PART 1 SYNCHRONIZATION

• When the receiver wakes up, it takes the next
  sequence that is coming in and seeds the LFSR
  with that word. This yields just one error due
  to synchronization of the LFSRs.

• If a legitimate error occurs, the Error Counter
  will be incremented. Saturation is reached when
  the counter gets to 15. In this case, the last
  word received will be used as the new seed, and
  the counter cleared.

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EXTRA PART 2 TRUE 8-BIT SEQUENCE

• Original Vector 00011101

0
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EXTRA PART 2 TRUE 8-BIT SEQUENCE
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OPERATION FREQUENCY AND FUTURE WORK
BRG TXBERT
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QUESTIONS ?