Processor%20Acceleration%20Through%20Automated%20Instruction%20Set%20Customization

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Processor Acceleration Through Automated
Instruction Set Customization

• Nathan Clark, Hongtao Zhong, Scott Mahlke
• Advanced Computer Architecture Lab
• University of Michigan, Ann Arbor
• December 3, 2003

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Motivation

• Cell phones, PDAs, digital cameras, etc. are
  everywhere
• High performance yet low power design point
• General core ASIC solution
• Limited post-programmability
• General core application specific instructions
  (CFUs)

CPU
CFU
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What is a CFU?

• Combine multiple primitive operations
• Smaller code size, fewer RF reads
• Increases performance

CFU 1
1
1
2



2
1
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Automation is Key

• This is ¼ of the DFG for a single basic block of
  blowfish

159 XOR
164 SHR
173 AND
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Related Work

• Tensilica Xtensa
• Commercial example
• MIPS core manually constructed CFU
• Automatic instruction set synthesis is mature
  field
• See paper for comparison of techniques
• Our contributions
• Novel technique for automatic CFU creation
• System to utilize CFUs in multiple applications
• Analysis of how effectively CFUs for one
  application apply to other applications in the
  same domain

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System Overview

• Synthesis
• Subgraph identification
• Discover candidates for CFUs
• Weed out what shouldnt be picked
• Selection
• Determine which candidates to use as CFUs
• Compilation
• Subgraph replacement
• Make use of the CFUs in a range of applications

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Subgraph Identification

• Grow subgraphs from seed nodes
• All nodes are seeds
• Most directions dont make sense
• How to decide where to grow?
• Making decisions using factors similar to an
  architect
• Take 4 factors into consideration
• Criticality, Latency, Area, Input/Output

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Subgraph Identification

• Grow subgraphs from seed nodes
• All nodes are seeds
• Most directions dont make sense
• How to decide where to grow?
• Making decisions using factors similar to an
  architect
• Take 4 factors into consideration
• Criticality, Latency, Area, Input/Output

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CFU Candidates

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Subgraph Identification

• Grow subgraphs from seed nodes
• All nodes are seeds
• Most directions dont make sense
• How to decide where to grow?
• Making decisions using factors similar to an
  architect
• Take 4 factors into consideration
• Criticality, Latency, Area, Input/Output
• Sum of these factors determines value of each
  direction
• NOT picking CFUs

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CFU Candidates


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Critical Path

• Combining operations on the critical path will
  shrink the longer dependence chains
• Maximize potential performance gain
• Wt
• Slack is cycles off longest dependence path

10/(01) 10
10/(21) 3.33
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Latency

• Growing toward low latency operations allows
  combination of more nodes in a cycle
• Maximize DFG compression
• Wt

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100.3 / 0.36 8.33



Opcode Area Cycles
1.00 0.30
0.12 0.06
ltlt, gtgt 0.01 0.00
0.16 0.09
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100.3 / 0.6 5




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Area

• Want the most benefit for the least area
• Wt
• Area is the sum of macrocell areas

100.5/0.5 10
100.5/1.5 3.33
Opcode Area Cycles
1.00 0.30
0.12 0.06
ltlt, gtgt 0.01 0.00
0.16 0.09
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Input/Output

• Want CFUs to use as few RF ports as possible
• Smaller encoding
• Allow growth of larger candidates
• Wt

102/(41) 4
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102/(21) 6.67



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Example


28.5
35

30.8
37.5
28.5
37.5
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Example


28.5
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30.8
28.5
40
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33.5






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Example


28.5
35

30.8
28.5
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36
36






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Example



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Example



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Example



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Example



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Example



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Example



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Example



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Finished Met External Constraints
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Set of Candidates







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Avoids Exponential Explosion
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Greedy Selection Heuristic

• Use estimates of performance improvement / cost

Subgraph Number Value Cost Ops
1 20 4 (3,4),(6,8)
2 6 1 (1,3,7)

N 9 5 (1,7)
Subgraph Number Value Cost Ops
1 10 4 (6,8)
2 6 1 (1,3,7)

N 0 5
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Compiler Replacement

• Multiple applications can utilize CFUs
• Vflib pattern matcher Cor 99

Instruction Synthesis
CFU Description
Compiler
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Experimental Setup

• Implemented in the Trimaran toolset
• Baseline machine 1 Int, 1 Flt, 1 Br, 1 Mem/Cycle
• CFUs use Int issue slot
• CFU latency/area generated as sum of each
  individual macrocell
• Pipeline latches were added if CFU latency gt1
  clock cycle
• 300 MHz clock assumed
• No branch or memory instructions in CFUs
• Four application domains tested
• Audio, Encryption, Image, Network

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Native Encryption Results
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Encryption Cross Compile
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Generalizing CFUs
Subsumed (Multiple Paths)
Wildcards (Multiple Nodes)
IN_1
0x8, 0x0
IN_1
0x8
gtgt
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0xF, 0x0
0xF

,
IN_2
IN_2

,-
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Effects of Generalization
Speedup
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Conclusions

• Developed two phase instruction set synthesis
  system
• Guide function removes bad candidates
• Greedy selection heuristic
• Substantial speedups can be attained with very
  little die impact
• Subsumed subgraphs and wildcarding increase
  cross-application effectiveness

Domain Encryption Network Image Audio
Ave. Speedup 1.61 1.38 1.16 1.66
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Questions?
http//cccp.eecs.umich.edu
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Backup slides
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Individual Factors - Blowfish
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Individual Factors - Djpeg
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Selection

• Uses estimates of performance improvement
• Greedy Heuristic used

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