Avoiding Initialization Misses to the Heap

1
Power-Aware Operand Delivery Erika Gunadi and
Mikko H. Lipasti University of Wisconsin - Madison
ARFPL
ARFnoPL
PRFPL
PRFPL
Rename
wr RAT re RAT
wr RAT re RAT
wr RAT re RAT
wr RAT re RAT
Read
re ARF re ROB
re PRF
Queue
wr RS, wr PL wr ROB
wr RS, wr PL wr ROB
wr RS, wr PL wr ROB
wr RS, wr PL wr ROB
Sched
wr RS
wr RS
wr RS
wr RS
Issue
re PL
re PL
re PL
re PL
Read
re ARF re ROB
re PRF
Exe
execute
execute
execute
execute
WB
wr ROB, wr RAT wr PL
wr ROB wr RAT
wr PRF, wr RAT wr PL
wr PRF wr RAT
Retire
re ROB, wr ARF wr RAT
re ROB, wr ARF wr RAT
re ROB
re ROB
ARF
PRF
Intel P6, Intel Core, Intel Pentium M, AMD K8
(Athlon, Opteron)
None
Payload RAM (PL)
No Payload RAM (noPL)
None
Intel Pentium 4, MIPS R10K, Alpha 21264, IBM
Power4, Power 5
ARF
ROB
PRF
PLRAM
ARF
ROB
PLRAM
PRF
ALU
ALU
ALU
ALU
ARF with Payload RAM
ARF with no Payload RAM
PRF with Payload RAM
PRF with no Payload RAM