4446 Design of Microprocessor-Based Systems

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4446 Design of Microprocessor-Based Systems
Memory Interface
Dr. Esam Al_Qaralleh CE Department Princess
Sumaya University for Technology
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Connections Between CPU and Memory
Control signals
Memory
8088
Data Bus
Address bus

• What are the control signals from the
  microprocessor to memory? What are the
  control signal from memory to the microprocessor?

• Address and data signals should be buffered

• The use of buffers on address bus increases
  driving capability
• Bi-directional buffers are used to control the
  data transferring directions on data bus
• D latches are used to de-multiplex signals on
  AD70 (and A1916)

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Timing Diagram of A Memory Operation

• Example 8088 sends address 70C12 to memory in a
  memory read operation
• assume that data 30H is read

T3
T4
T1
T2
CLK
Addr150
D latch
ALE
8088
A158
A1916
7H
S3-S6
Buffer
A158
0CH
AD70
Memory
D latch
AD70
12H
30H
D70
Trans -ceiver
Addr1916
7H
DT/R
DEN
Addr158
0CH
IO/M
Addr70
12H
WR
RD
30H
D70
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11.3 Bus Buffering
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Memory Chips

• The number of address pins is related to the
  number of memory locations .
• Common sizes today are 1K to 256M locations. (10
  and 28 address pins are present.)
• The data pins are typically bi-directional in
  read-write memories.
• The number of data pins is related to the size of
  the memory location .
• For example, an 8-bit wide (byte-wide) memory
  device has 8 data pins.
• Catalog listing of 1K X 8 indicate a byte
  addressable 8K memory.
• Each memory device has at least one chip select (
  CS ) or chip enable ( CE ) or select ( S ) pin
  that enables the memory device.
• Each memory device has at least one control pin.
• For ROMs, an output enable ( OE ) or gate ( G )
  is present.
• The OE pin enables and disables a set of tristate
  buffers.
• For RAMs, a read-write ( R/W ) or write enable (
  WE ) and read enable (OE ) are present.
• For dual control pin devices, it must be hold
  true that both are not 0 at the same time.

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Memory Address Decoding

• The processor can usually address a memory space
  that is much larger than the memory space covered
  by an individual memory chip.
• In order to splice a memory device into the
  address space of the processor, decoding is
  necessary.
• For example, the 8088 issues 20-bit addresses for
  a total of 1MB of memory address space.
• However, the BIOS on a 2716 EPROM has only 2KB of
  memory and 11 address pins.
• A decoder can be used to decode the additional 9
  address pins and allow the EPROM to be placed in
  any 2KB section of the 1MB address space.

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Memory Address Decoding
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Memory Map -
All the address lines used by the decoder or
memory chip gt each byte is uniquely addressed
full address decoding
Full address decoding
FFFFF 00000
FFFFF 3FFFF 00000
FFFFF FC000 3FFFF 00000
FFFFF FC000 83FFF 80000 3FFFF 00000
FFFFF FC000 9FFFF 9C000 83FFF 80000 3FFFF
00000
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Decoding Circuits

• NAND gate decoders are not often used.
• 3-to-8 Line Decoder (74LS138) is more common.

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Memory Address Decoding

• Using Full memory addressing space

Addr190
FFFFF
0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1
Highest address
37FFF
32KB
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
Lowest address
30000
These 5 address lines are not changed. They set
the base address
These 15 address lines select one of the 215
(32768) locations inside the RAMs
00000
Can we design a decoder such that the first
address of the 32KB memory is 37124H?
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Memory Address Decoding

• Design a 1MB memory system consisting of
  multiple memory chips

• Solution 1

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Memory Address Decoding

• Design a 1MB memory system consisting of
  multiple memory chips

• Solution 2

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Memory Address Decoding

• Design a 1MB memory system consisting of
  multiple memory chips

• Solution 3

It is a bad design, but still works!
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Memory Address Decoding

• Design a 1MB memory system consisting of
  multiple memory chips

• Solution 4

256KB
256KB
512KB
CS
CS
CS
Addr170
Addr18
Addr18
Addr19
IO/M
Addr19
Addr18
Addr19
IO/M
IO/M
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Memory Address Decoding

• Exercise Problem

• A 64KB memory chip is used to build a memory
  system with the starting address of 7000H.
  A block of memory locations in the memory chip
  are damaged.

FFFFH
7FFFFH
733FFH
3317H
73317H
Replace this block
3210H
73210H
73200H
0000H
70000H
64KB
Damaged block
1M addressing space
1M addressing space
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Memory Address Decoding
64KB
A150
512B
A80
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Memory Address Decoding

• Exercise Problem

• A 2MB memory chip with a damaged block (from
  0DCF12H to 103745H) is used to build a 1MB
  memory system for an 8088-based computer

1FFFFFH
1FFFFFH
512K
180000H
103745H
Use these two blocks
0FFFFFH
0DCF12H
07FFFFH
512K
000000H
000000H
Damaged block
A20
A19
A190
A190
CS
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Memory Address Decoding

• Partial decoding

• Example

• build a 32KB memory system by using four 8KB
  memory chips

• The starting address of the 32KB memory system
  is 30000H

0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
high addr. of chip 4
0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0
Low addr. of chip 4
0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1
high addr. of chip 3
Chip 4
0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0
36000H
Low addr. of chip 3
Chip 3
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1
34000H
high addr. of chip 2
0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0
Chip 2
Low addr. of chip 2
32000H
Chip 1
0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
1
30000H
high addr. of chip 1
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Low addr. of chip 1
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Memory Map -
Some address lines not used by the decoder or
memory chip gt mirror images partial address
decoding
Partial address decoding
FFFFF 00000
FFFFF 3FFFF 00000
FFFFF 3FFFF 30000 2FFFF 20
000 1FFFF 10000 0FFFF 00000
FFFFF FC000 7FFFF 7C000 3FFFF
30000 2FFFF 20000 1FFFF 10000 0FFFF 00000
FFFFF FC000 9FFFF 9C000 83FFF 80000 7FF
FF 7C000 3FFFF 30000 2FFFF 20000 1FFFF 10000
0FFFF 00000
FFFFF FC000 DFFFF DC000 CF000 CC000 9FFFF 9C
000 83FFF 80000 7FFFF 7C000 3FFFF 30000 2FF
FF 20000 1FFFF 10000 0FFFF 00000
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Memory Address Decoding

• Implementation of partial decoding

• With the above decoding scheme, what happens if
  the processor accesses location 02117H,
  32117H, and 9A117H?
• If two 16KB memory chips are used to implement
  the 32KB memory system, what is the partial
  decoding circuit?
• What are the advantage and disadvantage of
  partial decoding circuits?

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Generating Wait States

• Wait states are inserted into memory read or
  write cycles if slow memories are used in
  computer systems
• Ready signal is used to indicate if wait states
  are needed

data
memory
Address
8088
Delay circuit
decoder
Ready
Ready
clr
clr
clk
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Generating Wait States (Timing)
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Memory System
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Introduction

• To store a single bit, we can use
• Flip flops or latches
• Larger memories can be built by
• Using a 2D array of these 1-bit devices
• Horizontal expansion to increase word size
• Vertical expansion to increase number of words
• Dynamic RAMs use a tiny capacitor to store a bit
• Design concepts are mostly independent of the
  actual technique used to store a bit of data

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Memory Design with D Flip Flops

• An example
• 4X3 memory design
• Uses 12 D flip flops in a 2D array
• Uses a 2-to-4 decoder to select a row (i.e. a
  word)
• Multiplexers are used to gate the appropriate
  output
• A single WRITE (WR) is used to serve as a write
  and read signal
• zero is used to indicate write operation
• one is used for read operation
• Two address lines are needed to select one of
  four words of 3 bits each

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Memory Design with D Flip Flops (contd)
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Memory Design with D Flip Flops

• Problems with the design
• Requires separate data in and out lines
• Cannot use the bidirectional data bus
• Cannot use this design as a building block to
  design larger memories
• To do this, we need a chip select input
• We need techniques to connect multiple devices to
  a bus

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Techniques to Connect to a Bus

• Three techniques
• Use multiplexers
• Example
• We used multiplexers in the last memory design
• We cannot use MUXs to support bidirectional buses
• Use open collector outputs
• Special devices that facilitate connection of
  several outputs together
• Use tri-state buffers
• Most commonly used devices

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Techniques to Connect to a Bus
Open collector technique
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Techniques to Connect to a Bus
Tri-State Buffers
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Techniques to Connect to a Bus
Two example tri-state buffer chips
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Building a Memory Block
A 4 X 3 memory design using D flip-flops
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Building Larger Memories
2 X 16 memory module using 74373 chips
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Designing Larger Memories

• Issues involved
• Selection of a memory chip
• Example To design a 64M X 32 memory, we could
  use
• Eight 64M X 4 in 1 X 8 array (i.e., single row)
• Eight 32M X 8 in 2 X 4 array
• Eight 16M X 16 in 4 X 2 array
• Designing M X N memory with D X W chips
• Number of chips M.N/D.W
• Number of rows M/D
• Number of columns N/W

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Designing Larger Memories
64M X 32 memory using 16M X 16 chips
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Memory Mapping
Full mapping
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Memory Mapping (contd)
Partial mapping
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Interleaved Memory

• In our memory designs
• Block of contiguous memory addresses is mapped to
  a module
• One advantage
• Incremental expansion
• Disadvantage
• Successive accesses take more time
• Not possible to hide memory latency
• Interleaved memories
• Improve access performance
• Allow overlapped memory access
• Use multiple banks and access all banks
  simultaneously
• Addresses are spread over banks
• Not mapped to a single memory module

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Interleaved Memory (contd)

• The n-bit address is divided into two r and m
  bits
• n r m
• Normal memory
• Higher order r bits identify a module
• Lower order m bits identify a location in the
  module
• Called high-order interleaving
• Interleaved memory
• Lower order r bits identify a module
• Higher order m bits identify a location in the
  module
• Called low-order interleaving
• Memory modules are referred to as memory banks

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Interleaved Memory (contd)
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Interleaved Memory (contd)

• Two possible implementations
• Synchronized access organization
• Upper m bits are presented to all banks
  simultaneously
• Data are latched into output registers (MDR)
• During the data transfer, next m bits are
  presented to initiate the next cycle
• Independent access organization
• Synchronized design does not efficiently support
  access to non-sequential access patterns
• Allows pipelined access even for arbitrary
  addresses
• Each memory bank has a memory address register
  (MAR)
• No need for MDR

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Interleaved Memory (contd)
Synchronized access organization
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Interleaved Memory (contd)
Interleaved memory allows pipelined access to
memory
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Interleaved Memory (contd)
Independent access organization
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Interleaved Memory (contd)

• Number of banks
• M memory access time in cycles
• To provide one word per cycle
• Number of banks ? M
• Drawbacks of interleaved memory
• Involves complex design
• Example Need MDR or MAR
• Reduced fault-tolerance
• One bank failure leads to failure of the whole
  memory
• Cannot be expanded incrementally

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1. Static RAM (SRAM)

• Essentially uses flip-flops to store charge
  (transistor circuit)
• As long as power is present, transistors do not
  lose charge (no refresh)
• Very fast (no sense circuitry to drive nor charge
  depletion)
• Complex construction
• Large bit circuit
• Expensive
• Used for Cache RAM because of speed and no need
  for large volume

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Static RAM Structure
1
NOT
0
1
six transistors per bit (flip flop)
1
0
example
0/1
1
0
0
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2. Dynamic RAM (DRAM)

• Bits stored as charge in capacitors
• Simpler construction
• Smaller per bit
• Less expensive
• Slower than SRAM
• Typical application is main memory
• Essentially analogue -- level of charge
  determines value

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Dynamic RAM Structure
High Voltage at Y allows current to flow from
X to Z or Z to X
Y
X
Z

one transistor and one capacitor per bit
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SRAM v.s. DRAM
Static Random Access Memory (SRAM)
Dynamic Random Access Memory (DRAM)
Storage element

1. Fast
2. No refreshing operations

1. High density and less expensive

Advantages

1. Large silicon area
2. expensive

1. Slow
2. Require refreshing operations

Disadvantages
High speed memory applications, Such as cache
Applications
Main memories in computer systems
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DRAM Organisation

• Two dimensional matrix
• Bits are accesses by

• Accepting row and column addresses down the same
  multiplexed address bus

• First Row address is presented and latched by
  ras signal
• Next column address is presented and latched by
  cas signal

cas
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Typical 16 Mb DRAM (4M x 4)
RAS Row Addr. Select CAS Column Addr. Select
WE Write Enable OE Output Enable
2 k x 2 k 4 M
nybble
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Accessing DRAMs

• DRAM block diagram

CAS
Addr70
Column decoder
Storage Array
RAS
Row decoder
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Accessing DRAMs

• Address bus selection circuit

Row Address
To DRAM
MUX
Column Address
RAS
CAS
decoder
Q
D
Q
D
Q
D
address
Q
set
set
set
CLK
IO/M
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Accessing DRAMs

• Refreshing operations

• Because leakage current will destroy information
  stored on DRAM capacitors periodic
  refreshing operations are required for DRAM
  circuits
• During refreshing operation, DRAM circuit are
  not able to response processors request to
  perform read or write operations
• How to suspend memory operations?
• DRAM controllers are developed to take care DRAM
  refreshing operations

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