ALICE

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ALICE PMD Front-End Electronics (FEE)
S. Ramanarain and J. Saini
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Sept 2007
Readout Architecture
CROCUS Crate .
DAQ
Bottom PCB
Optical link DDL 100 meter.
HONEYCOMB
Top PCB
Link to download Pedestals. DSP code.
FEE 12
Optical link DDL 100 meter.
CRT
FRT
PC
Back Plane PCB
SOFTWARE
Ribbon cable 40 meter
TCI One crate for all CROCUS.
FEE 1

• For PRE
• Each CHAIN in PRE consists of 12 FEE boards
• Number of CHAINs in each module 6
• Number of CHAINs in PRE plane 24x6144
• For CPV
• Long type each CHAIN has 24 boards
• Long type number of CHAINs each module 3
• Number of CHAINs in Long type 12x336
• Short type 2 CHAINS with 24 boards, 2 CHAINS
  with 12 boards
• Short type 4 CHAINS/module
• Number of CHAINS in Short type12x448
• Total number of CHAINs 1443648228
• Each CROCUS has 5 FRT s.
• Each FRT reads 10 patch (Chains) buses.
• EACH CROCUS reads 50 chains. 6 CROCUS (PRE4,
  CPV2)

Translator
Patch Bus
SC
LV
HV
FTD
TTCrx
FFT

Total no of cells 221184
Total no of Modules 48 1 module
4608 cells read 1 module read by 72 FEE boards 1
FEE board 64 cells (4 MANAS Chips). Each
MANAS reads 16 channels

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FEE BOARD
FEE Board
1) Reads 64 analog signals (honeycomb cells) from
the detector. 2) Converts Analog to digital by
serial 12 bit , ADCS (AD7476). 3) The 4 MANAS
Chips and 2 ADCS are controlled by MARC (MUON ARM
READOUT CHIP). 4) MANAS is 16 channels
Multiplexed AN alog And Signal Processor. 5)
Communicates with DSP (CROCUS -DAQ) through LINK
PORT BUS (4 bit) 6) 16 MHZ crystal ( not shown
here) for MARC .
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MANAS Block diagram .
Introduction
Cells
Specs 1) Sensitivity 3mv/fc
2) Peaking Time
1.2 Micro sec. (3) Dynamic Range POS ()
500 fc , (4)Power consumption
7 mw /channel
NEG ( - ) 280 fc
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MANAS Features

• MANAS has 16 input channels and one output
  channel. Input signals after processing are
  available at the output through output
  multiplexed.
• 1) CSA (charge sensitive amplifier) integrates
  input charge collected, on its feed back
  capacitance. Decay time
• constant 20 micro sec for max charge
  collection.
• 2) Signal From gas detectors contains hyperbolic
  tail tail due slow motion of ions . The
  DECONVOLUTION filter (DF) removes this long tail
  and ensures base line restoration . The long tail
  also hinders high count rates.
• 3) The SGS i.e Semi Gaussian Shaper (SGS) shapes
  the pulses to Semi Gaussian which is essential to
  avoid pile up.Improves S/N ratio and ensures
  faster base line restoration.The time constant
  of the shaper is kept large to avoid ballastic
  deficit and ensure max charge collection.
• 4) A properly timed T/Hold pulse opens the
  switch (OFF) at the instant when peak of the
  input signal arrives .
• The capacitor then holds the peak
  amplitude of the signal which is a measure of
  input charge.In the switch ON condition the the
  capacitor tracks the input signal from shaper.
• 5) Analog multiplexer consists of 16 switches .
  Output of these switches are connected together
  and this line forms output line from the chip.
  Switches are controlled by CLK signals.
• 6) Once the readout is completed RESET is
  generated.

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MARC BLOCK diagram
MARC 1) Controls 4 MANAS Chips- generates CLK,
CLR, T/Hold for MANAS on receipt of Trigger. 2)
Controls 2 (serial) ADCS 12 bit by generating
Chip select and reading from ADC by sending SCLK
3) Threshold Values are stored in a 64 word 12
bit RAM. 4) 12 bit ADC words are stored in
temporary register (Shift Reg) and compared with
RAM words. 5) Data above threshold are stored
in 64 word 18 bit FIFO together with 6 bit
channel Address ( 6 bit for 64 channels) 6) The
6418 bit merged with 11 bit module address (FEE)
along with one Parity and 2 control, bits forming
32 bit word. 7) The resulting 32 bit word sent
through Link port as 8 nibbles of 4 bits each.
8) Performs zero suppression on DATA. 9)
Communicates with ADSP 2106N through 4 bit bus
I.e Link port bus.
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Chain with 12 FEE Boards
Translator 1) Signals from FEE boards are LVTTL
type. Translator converts all LVTTL signals from
FEE boards i.e 4 data bits Do-D3 and CLK,
Token Back to LVDS levels (LOW VOLTAGE
DIFFERENTIAL SIGNALS) before going to CROCUS. 2)
It also translates all LVDS signals from CROCUS
i.e TRIG,RESET,LDCLK, LDDATA,ACKL, TOKEN IN
, EN to LVTTL (Low voltage TTL). 3) On the
patch Bus all signals are LVDS. CAL signal is
analog signal for calibration. 4) Low voltage to
the chain (12/24 boards) is fed through
Translator and Bridge boards. 5) Trim pots for
adjusting threshold levels of signals. 6)
Connected to Bridge board by FLEXIBLE PCB for
reading 24 boards..
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Testing with Bridge board
LPACK,CLKLD,DATALD,TRIG.MR,CAL
LVDS
EN
FEE12
VCC
BRIDGE BOARD
Patch bus
Token In 0
TOKENIN1
Token
FEE1
Token
FEE13
FEE24
TRANS
TKBACK0
GND
TKBACK1
LPCLK, LPDO, LPD1,LPD2, LPD3
Bridge Board 1) Enables reading of 24 boards
by using a digital buffer. LV to second
section through BRIDGE board. 2) Each section
needs 2 tokens. Token back signals go to
Translator and finally to CROCUS as Token
BACK. 3) Readout of second section by sending
enable signal. While reading first section
it is disabled. 4) Trim pots For adjusting
threshold levels of Signals. 5) Connected to
translator by a FLEXIBLE PCB for reading 24
boards.
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24 boards on UM-long, Back plane PCB
UM-long
FEE
FEE
LVTTL bus
LV
TB
BB
Flexible link
Patch Cable
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Testing Of boards
HP 81110A Pulse Generator
Signal cables
Zone of 64 cells (322)
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Typical pedestal calibration plots
Pedestal for 64 channels
Gain calibration Plots.
RMS for 64 channels
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Comparison plot with internal external
capacitance
External capacitor
Input calibration pulse
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HV -LV Components
SY 1527
1821-N 12 Ch HV
45 Volts PWR module for EASY 3000
3025-B
3009-B
EASY- 3000
LV modules
1676 A- Branch controller
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LOW VOLTAGE Distribution
3009B
3025B
Controls
3.3V for CROCUS from 3025-B
/- 2.5V for FEE, 3.3 V for MARC from 3009-B
12 Modules - 3009B for 48 DB s 48 DB s -
288 chains (12 FEE)
2 Modules - 3025 B - 8 channels 6 For
CROCUS, 2 spare
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Low Voltage Distribution
Basic circuit
LOAD
P-Channel
N-Channel
S
S
500ns
G
G
D
D
RST
MAX 4373
MAX 4373
R sense
R sense
V in
-V in
Control Logic
LVDB
ELMB
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CRATE ARRANGEMENT
EASY3000-1
EASY3000-2
EASY3000-3
3009B
3009B
3009B
3009B
3009B
3009B
3009B
3009B
3009B
3009B
3009B
3009B
Max Power 1500W
Max Power 1500W
Max Power 1500W
EASY3000-4
Max Power 540W
3025B
3025B
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STATUS OF FEE AS ON APR 07

• Translator (300 No) and Bridge board (70 No)
  assembly completed.
• Testing of these boards is being done along with
  FEE boards.
• Assembly of 4000 FEE boards completed. Testing
  and calibration
• being done. Expected time three months.
• 4) Back plane PCBs (50 No) for LONG and SHORT
  types expected by MAY 07.
• Low voltage Distribution PCBs expected by MAY -07
  END.
• Signal cables for FEE , TB to BB being ordered.
• LV Cables, Patch panels, Patch bus cables,
  connectors, tools being procured.
• CROCUS assembly being processed but delayed due
  to procurement of
• connectors.