Noise Canceling in 1D Data: Presentation

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Mar 28rd, 2005 Chip Level Layout 2
Noise Canceling in 1-D Data Presentation 10
Seri Rahayu Abd Rauf Fatima Boujarwah Juan
Chen Liyana Mohd Sharipp Arti Thumar
M2
Project Manager Bobby Colyer
Overall Project Objective Implementing Noise
Cancellation Algorithm in Hardware
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Status

• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
• - Schematics (Done)
• To be done
• Layout (93)
• Spice simulation (85)

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Design Decisions

• Redesigned the bottom fpAdder to better fit the
  new floorplan.
• Changed the wiring of the inputs and outputs of
  the toplevel registers and muxes.

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Previous Floorplan
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New and Improved Floorplan
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Layer Masks - Poly
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Layer Masks - Metal 1
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Layer Masks Metal 2
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Layer Masks Metal 3
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Layer Masks Metal 4
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The Chip

• Dimension
• Width 377.19µ
• Height 303.3450µ
• Area 114418.701µ²
• Transistor count 25859
• Density 0.226 trans/µ²
• Aspect ratio 1 1.24

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Floating Point Multiplier
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10-bit Wallace Tree Multiplier
20 bit output
2 10-bit inputs
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Side components of the Multipliers
Output
Side
Center
Inputs
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fpMult Simulation Results (Extracted RC)
Bits 8-15
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Simulation Results (Schematics with Load Caps)
Bits 8-15
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Floating Point Adder
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fpAdder Components
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AlignShift Simulation Results (ExtractedRC)
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Registers

• 2 types of registers

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16 bit Register Simulation Results (ExtractedRC)
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16 bit Register Simulation Results (Schematic)
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16-bit 2-1 Mux
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Simulation Results (ExtractedRC)
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Simulation Results (Schematics with Load)
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ROM
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Simulation Results (Schematics with Load)
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ROM Analysis

• Rise Time 672.21 ps
• Fall Time 620.4 ps

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• Questions?