CSE 242A Integrated Circuit Layout Automation

1
CSE 242A Integrated Circuit Layout Automation

• Lecture 1 Introduction
• Winter 2009
• Chung-Kuan Cheng

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Agenda

• Introduction to CSE242A class
• Topics
• Class assignments and projects
• Design challenges
• ITRS Roadmap

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Topics of CSE242A

• ITRS Roadmap and Low Power Design Methodologies 
• Partitioning (1) Two way partitioning, (2)
  Multiple way partitioning, (3) Multiple level
  partitioning, (4) Replication cuts, (5)
  Performance-driven partitioning, (6) Partitioning
  for FPGAs.
• Floorplanning (1) Floorplanning representations,
  (2) Block configurations, (3) 3D floorplanning.
• Placement (1) Placement algorithms, (2) Local
  placement, (3) Performance driven placement.
• Global Routing (1) Multi-commodity flows, (2)
  Steiner Trees, (3) Performance driven routing.
• Detail Routing (1) Channel routing, (2) Maze
  routing, (3) PC board routing.
• Special Net Routing (1) Bus routing, (2) Clock
  networks, (3) Net matching, (4) Power/Ground
  distributions.
• Cell Layout, Compaction.

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Class Assignments

• Homeworks
• Projects
• Divided into phases
• Report and presentation

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Design Challenges

• Parallel Processing
• Power Dissipation
• New Technologies

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Theme of Class

• Combinatorial Algorithms
• Formulation
• Engineering
• Electronic Circuits
• Physics

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Scaling

• Power
• Interconnect dominance
• Current density
• Copper resistivity increases

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New Technologies

• 3D Extension
• Heterogeneous System
• Low K
• New Tech
• Optical
• Carbon Nano Tube (CNT)
• Atomic Switch
• Spintronics

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Moores Law

• Trans 2 / 18 months
• Product price drop half every 18 month

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ITRS Roadmap 2007
2007 2010 2013 2016 2019 2022
DRAM ½ pitch (nm) 65 45 32 22 16 11
MPU/ASIC m1 ½ pitch 68 45 32 22 16 11
High Volumn MPU Chip Size (mm2 ) 140 140 140 140 140 140
Chip local clock (GHz) 4.7 5.87 7.34 9.18 11.47 14.34
High Performance Vdd 1.1 1.0 0.9 0.8 0.7 0.65
Low Power Vdd 0.8 0.7 0.6 0.5 0.5 0.45