CS2100 Computer Organisation http:www'comp'nus'edu'sgcs2100

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CS2100 Computer Organisationhttp//www.comp.nus.e
du.sg/cs2100/

• Input/Output
• (AY2007/8) Semester 2

Adapted from David Patternsons lecture slides
http//www-inst.eecs.berkeley.edu/cs152/
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THE BIG PICTURE
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INPUT/OUTPUT DEVICES
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WHY I/O MATTERS?

• CPU performance increase 60 per year
• I/O performance increase lt 10 per year
• Limited by mechanical delays
• Amdahls Law system speedup is limited by the
  slowest part
• Example
• Suppose 1 sec I/O 4 sec CPU gt 5
  seconds
• Increase CPU performance by 100 gt 3 seconds
• We only get 66 speedup gt I/O
  bottleneck
• I think Silicon Valley was misnamed. If you look
  back at the dollars shipped in products in the
  last decade, there has been more revenue from
  magnetic disks than from silicon. They ought to
  rename the place Iron Oxide Valley. -- Al
  Hoagland, one of the pioneers of magnetic disks,
  1982

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TYPES AND CHARACTERISTICS OF I/O DEVICES

• Behavior
• Input read once
• Output write only, cannot be read
• Storage can be reread and usually rewritten
• Partner
• Whats on the other end? Human or machine
• Data Rate
• Peek rate of transfer between I/O and memory/CPU

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I/O DEVICE EXAMPLES
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MOUSE

• Invented by Douglas C. Engelbart (jointly with
  Bill English) in 1970
• SRI patented the mouse, but they really had no
  idea of its value. Some years later I learned
  that they had licensed it to Apple for something
  like 40,000. -- Douglas C. Engelbart
• Douglas was as a pioneer of human-computer
  interaction whose team developed hypertext,
  networked computers, and precursors to GUIs
• Mouse uses optimal or mechanical means to
  determine the X-Y coordinates
• Bandwidth requirement limited by human hand
  coordination
• We are too slow relative to the rate of reading
  mouse status

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MAGNETIC DISK

• Purpose
• Long term, nonvolatile storage
• Large, inexpensive, and slow
• Lowest level in the memory hierarchy
• Basic Idea
• Rely on a rotating platter coated with a magnetic
  surface
• Use a moveable read/write head to access the disk

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MAGNETIC DISK HISTORY
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HARD DISK DRIVE EVOLUTION
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MAGNETIC DISK

• Typical numbers (depending on the disk size)
• 500 to 2,000 tracks per surface
• 32 to 128 sectors per track
• A sector is the smallest unit that can be read or
  written
• Traditionally all tracks have the same number of
  sectors
• Constant bit density record more sectors on the
  outer tracks
• Recently relaxed constant bit size, speed varies
  with track location

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MAGNETIC DISK CHARACTERISTIC

• Cylinder all the tacks under the head
  at a given point on all surface
• Read/write data is a three-stage process
• Seek time position the arm over the proper track
• Rotational latency wait for the desired
  sectorto rotate under the read/write head
• Transfer time transfer a block of bits
  (sector)under the read-write head
• Average seek time as reported by the industry
• Typically in the range of 8 ms to 12 ms
• (Sum of the time for all possible seek) / (total
  of possible seeks)
• Due to locality of disk reference, actual average
  seek time may
• Only be 25 to 33 of the advertised number

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MAGNETIC DISK TYPICAL NUMBERS

• Rotational Latency
• Most disks rotate at 3,600 to 7200 RPM
• Approximately 16 ms to 8 ms per revolution,
  respectively
• An average latency to the desiredinformation is
  halfway around the disk 8 ms at 3600 RPM, 4 ms
  at 7200 RPM
• Transfer Time is a function of
• Transfer size (usually a sector) 1 KB / sector
• Rotation speed 3600 RPM to 7200 RPM
• Recording density bits per inch on a track
• Diameter typical diameter ranges from 2.5 to
  5.25 in
• Typical values 2 to 12 MB per second

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NETWORKS

• Medium to communicate between computers
• Characteristics
• Distance 0.01 to 10,000 km
• Speed 0.001 to 100 MB/sec
• Topology Bus, Ring, Star, Tree
• Examples
• RS232 standard star topology, slow
• LAN bus topology, 10 Mbit/sec

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I/O SYSTEM

• Bus is the connection between Processor, Memory
  and I/O
• Communication between Processor and devices is
  via bus protocols and interrupts

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BUSES

• Consists of control and data lines
• Control lines Signal requests and
  acknowledgments
• Data lines Carry information between the source
  and the destination
• Bus Transactions
• Sending the address
• Receiving or sending the data
• Advantages
• Versatility single connection scheme for easy
  add-ons
• Low cost single set of writes shared in multiple
  ways
• Disadvantages
• Communication bottleneck bandwidth limits the
  maximum I/O throughput
• Devices will not be able to use the bus when they
  need to

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TYPES OF BUSES

• Processor-Memory Bus (design specific)
• Short and high speed
• Only need to match the memory system
• Maximize memory-to-processor bandwidth
• Connects directly to the processor
• Optimized for cache block transfers
• I/O Bus (industry standard)
• Usually is lengthy and slower
• Need to match a wide range of I/O devices
• Connects to the processor-memory bus or backplane
  bus
• Backplane Bus (standard or proprietary)
• Backplane an interconnection structure within
  the chassis
• Allow processors, memory, and I/O devices to
  coexist
• Cost advantage one bus for all components

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A THREE-BUS SYSTEM

• A small number of backplane buses tap into the
  processor-memory bus
• Processor-memory bus is used for processor memory
  traffic
• I/O buses are connected to the backplane bus
• Advantage loading on the processor bus is
  greatly reduced

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EXAMPLE PENTIUM SYSTEM ORGANISATION
Processor/Memory Bus
PCI Bus Backplane
I/O Busses IDE, SCSI
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OBTAINING ACCESS TO BUS

• Bus Master Processor
• Controls access to bus
• Must initiate and control all bus requests
• Slave
• Responds to read and write requests
• Drawback of using single master
• Processor is involved in all requests
• Alternative schemes
• Multiple bus masters
• Mechanism for arbitrating access to the bus
  needed

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BUS ARBITRATION

• Bus arbitration scheme
• A bus master wanting to use the bus asserts the
  bus request
• A bus master cannot use the bus until its request
  is granted
• A bus master must release the bus back to the
  arbiter after finishing the transaction
• Bus arbitration schemes usually try to balance
  two factors
• Bus priority the highest priority device should
  be serviced first
• Fairness Even the lowest priority device should
  never be completely locked out from the bus

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GIVING COMMANDS TO I/O DEVICES

• Two methods are used to address the device
• Special I/O instructions
• Memory-mapped I/O
• Special I/O instructions specify
• Both the device number and the command word
• Device number the processor communicates this
  via aset of wires normally included as part of
  the I/O bus
• Command word this is usually send on the buss
  data lines
• Memory-mapped I/O
• Portions of the address space are assigned to I/O
  device
• Read and writes to those addresses are
  interpretedas commands to the I/O devices
• User programs are prevented from issuing I/O
  operations directly
• The I/O address space is protected by the address
  translation

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I/O DEVICE NOTIFYING THE OS

• The OS needs to know when
• The I/O device has completed an operation
• The I/O operation has encountered an error
• This can be accomplished in two different ways
• Polling
• The I/O device put information in a status
  register
• The OS periodically check the status register
• I/O Interrupt
• Whenever an I/O device needs attention from the
  processor,it interrupts the processor from what
  it is currently doing.

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POLLING PROGRAMMED I/O
busy wait loop not an efficient way to use the
CPU unless the device is very fast!
but checks for I/O completion can be dispersed
among computation intensive code

• Advantage
• Simple the processor is totally in control and
  does all the work
• Disadvantage
• Polling overhead can consume a lot of CPU time

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INTERRUPT DRIVEN DATA TRANSFER

• Advantage
• User program progress is only halted during
  actual transfer
• Disadvantage, special hardware is needed to
• Cause an interrupt (I/O device)
• Detect an interrupt (processor)
• Save the proper states to resume after the
  interrupt (processor)

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I/O INTERRUPT

• An I/O interrupt is asynchronous with respect to
  instruction execution
• I/O interrupt is not associated with any
  instruction
• I/O interrupt does not prevent any instruction
  from completion
• You can pick your own convenient point to take an
  interrupt
• I/O interrupt is complicated
• Needs to convey the identity of the device
  generating the interrupt
• Interrupt requests can have different urgencies
• Interrupt request needs to be prioritized

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DELEGATING I/O RESPONSIBILITY FROM THE CPU DMA

• Direct Memory Access (DMA)
• External to the CPU
• Act as a master on the bus
• Transfer blocks of data to or from memory without
  CPU intervention

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SUMMARY

• I/O performance is limited by weakest link in
  chain between OS and device
• Wide range of devices
• Bus hierarchy and arbitration
• I/O device notifying the operating system
• Polling it can waste a lot of processor time
• I/O interrupt similar to exception except it is
  asynchronous
• Delegating I/O responsibility from the CPU DMA

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