Power Comparison between Electrical and Optical

1
Power Comparison between Electrical and Optical
High-Speed Inter-Chip I/O Hoyeol Cho, Pawan
Kapur, and Krishna C. Saraswat Center for
Integrated Systems Stanford University, Stanford,
CA 94305 December 7th, 2002 Sponsored under the
contract from MARCO Interconnect Focus Center

• Optimization scheme to minimize optical link
  power including
• ASFP/Ideal modulator
• TIR (Trans-Impedance Receiver)
• Optical Transmission Medium with OPTE
• Quantification of the power dissipation for
  state-of-the-art
• high-speed electrical board level link
• Simultaneous bi-directional signaling
• Transmitter equalization
• On-chip noise cancellation
• Power comparison between electrical link and
  optical link power

2
Optical Link Modeling (I)

• Motivation
• An I/O bandwidth commensurate with a
  dramatically increasing on-chip computational
  capability is highly desirable
• Bandwidth using board-level copper interconnects
  may require large power and area due to
• complex signal processing (power may become
  substantial fraction of total power)
• Optical Interconnects can be a promising
  alternative to meet increasing I/O bandwidth
  demand, potentially at a lower power and area.

• Off-chip laser power source with 1.3mm
  wavelength monolithic integration of germanium
• photodetector directly onto silicon without
  causing noise in silicon circuits
• Off-chip source is distributed to various
  on-chip quantum well modulators (QWM) which can
  be either in InP system, bonded to silicon
  chip, or manufactured monolithically using Si/Ge
  QWs
• Trans-impedance receiver (TIR) with subsequent
  amplifier stages

3
Optical Link Modeling (II)

• Optical Modulator Power (QWM)
• Dynamic power due capacitance of modulator and
  the driving gates
• Static power optical absorption in QWs
  averaging on and off current multiplied by
  bias voltage

Popt average optical power at the receiver IL
insertion loss CR contrast ratio Vbias DC bias
applied to the modulator Vswing swing voltage
between on and off states OPTE optical power
transfer efficiency of the medium and couplers
O. Kibar et. al., J. Lightwave Technol., 1999

• Two types of modulators used
• Modulator1 Ideally off with small swing signal
  QWM (IL0.475, CR4.6) possible
• implementation using M. Whitehead et. al.,
  Electron., 1990
• Modulator2 Asymmetry Fabrey-Perot QWM O. Kibar
  et. al., J. Lightwave Technol., 1999
  (IL0.475, CR4.6 Vbias4.7V,
  VswingVdd for 100nm node)

• Receiver design
• Bit error rate (BER) 10-15 (SNR7.9) output
  voltage swing equal to the supplied voltage at
  a given bandwidth for particular technology node
  of ITRS
• Receiver power dramatically decreases with a
  decrease in the detector capacitance because
• of an increase in voltage swing ? reduce
  both power dissipation per stage (smaller width)
  as well as number of amplification stage ?
  initially assume pessimistically 250fF reduced
  to 50fF (practical)

4
Optical Link Optimization Result

• Optical Power Optimization
• Modulator power increases with increasing laser
  power
• Receiver power decreases with increasing laser
  power ? Optimum input laser power for minimum
  overall
• link power dissipation exists!
• Larger OPTE ? more power dissipated in
  transmitter
• Analysis can be used for both waveguide and free
  
• space link
• Polymer Waveguide link assumed Chen et. al.,
• Proc. IEEE, 2000 0.082dB/cm loss with
• theoretical analysis

• Technology node shrinks
• 100nm ? 50nm technology node (using same
• CR/IL/Vbias for transmitter) 1) Power
  dissipation decreases due to decrease in
• receiver power dissipation 2) Further
  reduction in overall power is possible if
• transmitter parameters for 50nm are
  applied

5
Electrical Link Modeling (I)

• Best available Board Level Electrical Signaling
  Options
• Differential Signaling 1) reduced signal
  return cross talk which provides zero return
  current with bipolar mode 2) enabled a
  noise-free receiver reference
• Bipolar Current Mode Signaling with high
  source impedance, enabled noise immunity to power
  supply
• Complete Residual ISI Cancellation using a
  transmitter side pre-emphasis equalization with
  multi-tap FIR filter
• On-chip Cancellation minimize the near-end
  reverse channel cross talk due to package
  reflections

Schematic showing board-level electrical links

• Reduce power dissipation in reference generation
  
• ? Reduce reference current 20 of the main
  transmitter current (increase reference resistor
  5 times)
• PKG model assume flip-chip package widely used
  in high-bandwidth application
• High performance GETEK board (loss tangent0.01)
  shown in following table

6
Electrical Link Modeling (II)

• Noise Source Modeling and Power Extraction
  Methodology
• The current swing was backtracked using the BER
  constraint (lt10-15), various noise sources
• Applying fixed noise and proportional noise with
  attenuation in PCB ? Swing voltage at transmitter
• Required current swing
• Bit rate increasesgt attenuation increases (A
  decreases) gt current swing increasesgt power
• dissipation increases

KA Attenuated proportional noise KU
Unattenuated proportional noise
?
The maximum bit rate-length contour for
simultaneous bi-directional signaling
Summary of the SPICE parameters used for
dielectric and skin effect loss
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Electrical Link Modeling (III)
Various Noise Sources for simultaneous
bi-directional signaling
SPICE simulation showing attenuation due to
electrical link

• Various Power dissipation Sources for High Speed
  Serial Link
• Termination resistance
• power dissipated in the two termination
  resistance
• power dissipated in the replica transmitter
  circuit resistance to cancel the opposite side
  transmitter signal
• Pre-emphasis Equalization
• 2 tap filter
• Receiver circuit transistors
• Transmitter circuit transistors
• On-chip Cancellation circuit resistor
  transistors

Ignored timing related power (DLL and clock) for
both electrical and optical links in this
analysis !
8
Electrical Link Power Dissipation Result

• Electrical Link Power Dissipation Results
• For 6Gbits/s bit rate, maximum link length
  50cm
• Most power is dissipated on the termination
  resistance
• Impact of connectors (Backplane involved)
• Additional connector noise must be included
• 1) Cross talk for uni-directional
  signaling (4.64) 2) Additional Cross
  talk due to bi-directional signaling (7.15)
  3) Parameters extracted with Teradyne VHDM
  HSD connector
• Power dissipation result with connectors
  (backplane involved)
• 1) overall power is dramatically
  increased from 5mW to 30mW
• at 20cm at 4Gbits/s with connectors
  (Fixed Noise 37.4mV)
• Impact of Fixed noise reduction Larger link
  length feasable for same power dissipation

Electrical link power dissipation vs. length
along with the breakdown without connector
Impact of fixed noise (Receiver sensitivity and
offset) reduction on power dissipation
Electrical link power dissipation vs. length
along with the breakdown with connector
Electrical link power dissipation vs. fixed noise
with connector
9
Power Comparison Optical Link vs. Electrical
Link(I)

• Power Comparison (pessimistic optical link
  capacitance)
• Bit rate6Gbits/s CLCoupling Loss
• Optical parameters 1) waveguide
  loss0.082dB/cm 2) Cdet250fF,
  Cmodulator100fF
• Electrical link without connector
• Critical length optical link yields lower power
  than electrical link
• increases with lower electrical fixed noise
  (quantified)
• decreases with decreasing CL and better
  modulator
• Optical link capacitance / Bit rate
• Critical length is substantially reduced as
  transmitter /receiver capacitance reduce
  (100fF/250fF ? 50fF/50fF )
• Critical length reduce at higher bit rate (4/6
  Gbits/s)

Power comparisons for different coupling losses
with modulator 1
Power comparisons for different coupling losses
with modulator 2
Power comparisons for two different bit rates
10
Power Comparison Optical Link vs. Electrical
Link(II)
Effect of coupling loss and detector/modulator
capacitance on critical length
Effect of modulators and detector/modulator
capacitance on power comparisons

• Conclusions and Ongoing
  Work
• Beyond a critical length, power optimized
  optical interconnects for high-speed I/O are
  shown to dissipate lower power compared to
  the state-of-the-art high-speed electrical
  signaling scheme
• The highest-end electrical receiver published to
  date (8.8mV fixed noise), the critical length is
  found to be about 35cm with low optical
  coupling losses and close to ideal modulator
• At higher bit rates critical length reduces and
  optics becomes more power favorable
• Including several factors, which were ignored in
  this electrical link analysis, such as dynamic
  power in logic for equalization and on-chip
  cancellation and rise time reduction induced
  greater package ringing at higher bit rates, will
  further reduce the critical lengths
• Inclusion of connector noise for backplane
  signaling will also deteriorate electrical link
  power with respect to high-speed optical
  links
• In process of including timing power, connector
  induced cross talk novel optical receivers and
  WDM