SpecC and SpecCharts

1
SpecC and SpecCharts

• Reviewed and Presented by
• Heemin Park and Eric Kwan
• EE202A - Fall 2001
• Professor Mani Srivastava

2
Overview

• Current problems in embedded systems development
• The solution SpecC / SpecCharts
• Key feature Program State Machine
• Highlight of SpecC
• Conclusion
• Questions

3
Current Design Problem

• Prototype debugging occupy 43 of development
  time
• Miscommunication of requirement
• Ambiguous specifications
• Absence of simulation and synthesis tool ?HUGE
  design loop
• The reason lack of a proper specification
  language

4
The solution SpecC SpecCharts

• Avoid miscommunication of requirement and
  incomplete / ambiguous specifications
• Proper specifications reduce debugging time by
  29
• Allow development of synthesis and simulation
  tools
• Simulate without building a prototype

Planning
Rapid Prototyping
Specification
Performance Evaluation
Implementation
AGILE DESIGN
Prototype
5
Design Flow using SpecC
Structure / Implementation detail
Order / Timing detail
SpecC
Untimed (causality)
Functional
Timed (estimated)
Structural
Bus- functional
Timing- accurate
Cycle- accurate
RTL/IS
6
Properties of embedded System

• VHDL support the following behavior of embedded
  systems
• Behavior Decomposition (Partial)
• Sequential Algorithm
• Behavior Completion (Partial)
• Not supported
• State Transition
• Exceptions

7
Why did others failed?
Characteristic SpecCharts SpecC VHDL Verilog Esteral State Charts
Behavioral decomposition Yes Yes Partial Yes Yes Yes
State Transition Yes Yes No No No Yes
Exception Yes Yes No Yes Yes Yes
Sequential algorithm Yes Yes Yes Yes Partial No
Behavioral completion Yes Yes Partial Yes Yes No
8
SpecCharts and SpecC

• Same Idea, different implementation
• SpecCharts is an extension to VHDL to tailored
  for embedded system design
• SpecC specification description language based
  on C
• Both implement the idea of a Program State
  Machine (PSM)

9
Program State Machine(PSM)

• Hierarchical/Concurrent FSM Programming
  language
• Program-state(PS)
• Status
• Inactive
• Executing
• Complete
• Computation
• Leaf
• Concurrent
• Sequential
• conditional transition arcs on completion or
  immediately

10
Program State Machine(Cont)

• SpecCharts
• PS described by procedures based on VHDL
• SpecC
• PS described by procedures in a programming
  language based on C

Sequential
Concurrent
Leaf
PSM model
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SpecChart Descriptions
behavior CheckCode type leaf is begin code_ok
lt true for (i in 1 to 4) loop wait
until tone / 1111 and toneevent if
(tone / user_code(i)) then code_on
lt false end if end loop end
Textual-version
Graphical-version
Transition on Complete(TOC)
Initial state
Complete state
Transition immediately(TI) (starts from boundary)
12
Design Flow using SpecCharts
SpecChart Descriptions
SpecCharts to VHDL translator
VHDL Codes
VHDL Simulator
VHDL Synthesizer
VHDL Verification tool
13
The SpecC Model

• Traditional model
• Processes and signals
• Mixture of computation and communication
• Automatic replacement impossible

• SpecC model
• Behaviors and channels
• Separation of computation and communication
• Plug-and-play

14
The SpecC Language

• ANSI-C
• Program is set of functions
• Execution starts fromfunction main()

/ HelloWorld.c / include ltstdio.hgt void
main(void) printf(Hello World!\n)

• SpecC
• Foundation ANSI-C
• Program is set of behaviors,channels, and
  interfaces
• Execution starts frombehavior Main.main()

// HelloWorld.sc include ltstdio.hgt behavior
Main void main(void) printf(Hello
World!\n)
15
The SpecC Language

• Basic structure
• Top behavior
• Child behaviors
• Channels
• Interfaces
• Variables (wires)
• Ports

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The SpecC Language

• Basic structure

interface I1 bit630 Read(void) void
Write(bit630) channel C1 implements
I1 behavior B1(in int, I1, out int) behavior
B(in int p1, out int p2) int v1 C1 c1
B1 b1(p1, c1, v1), b2(v1, c1, p2) void
main(void) par b1.main()
b2.main()
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The SpecC Language

• Behavioral hierarchy

Sequentialexecution
FSMexecution
Concurrentexecution
Pipelinedexecution
behavior B_pipe B b1, b2, b3 void
main(void) pipeb1.main() b2.main()
b3.main()
behavior B_seq B b1, b2, b3 void
main(void) b1.main() b2.main()
b3.main()
behavior B_fsm B b1, b2, b3, b4, b5, b6
void main(void) fsm b1 b2

behavior B_par B b1, b2, b3 void
main(void) parb1.main() b2.main()
b3.main()
18
Design Flow using SpecC
Structure / Implementation detail
Order / Timing detail
SpecC
Untimed (causality)
Functional
Timed (estimated)
Structural
Bus- functional
Timing- accurate
Cycle- accurate
RTL/IS
19
Conclusion

• SpecCharts
• PSM model of computation for embedded system
• VHDL base limited support for embedded software
• SpecC
• Well-known high-level language with support of
  PSM
• Design environment still developing
• Architecture exploration, refinement,
  communication synthesis,

20
Questions
21
References

• Literature
• Vahid, F. Narayan, S. Gajski, D.D. SpecCharts
  a VHDL front-end for embedded systems. IEEE
  Trans. on CAD, Vol.14(No.6), June 1995.
  Pp.694-706.
• SpecC Specification Language and Methodology, by
  Gajski, Zhu, Dömer, Gerstlauer, Zhao, Kluwer
  Academic Publishers, 2000.
• Circuits and Systems, 2001, Tutorial Guide ISCAS
  2001, The IEEE International
• The SpecC Language, pp.5.1_1-5.1_12.
• Modeling and Design with SpecC, pp.5.2_1-5.2_12.
• SpecC Design Environment, pp.5.6_1-5.6_4.
• SpecC Open Technology Consortium, pp.5.7_1-5.7_5.
• Online
• SpecC web pages at UCIhttp//www.cecs.uci.edu/sp
  ecc/
• SpecC Open Technology Consortium
  (STOC)http//www.specc.org/