EEL 6786 Advanced Networking Hardware Design Lecture 3 IP Router Architectures

1
EEL 6786Advanced Networking Hardware
DesignLecture 3 IP Router Architectures
Prof. Taskin Koçak School of EECS,
UCF tkocak_at_cs.ucf.edu Course URL
http//www.cs.ucf.edu/tkocak/eel6786.html
2
Introduction

• Based on the overview paper by James Aweya of
  Nortel Networks
• Routers have traditionally been implemented in
  software
• It is difficult to sustain wire-speed routing for
  high-speed traffic by software
• Due to advances in both networking and
  semiconductor technologies, it is possible to
  build single chip, low-cost routing solutions
  incorporating software and hardware

3
A generic router architecture
4
A generic router architecture (cont.)

• It typically consists of the controller card
  (holds CPU), router backplane, and interface
  cards.
• The CPU is responsible for path computation,
  table maintenance, etc..
• The interface cards include adapters that perform
  inbound and outbound packet forwarding
• The router backplane is responsible for
  transferring packets between the cards

5
Key router functions

• Route processing
• Routing table construction, maintenance using
  routing protocols, and updates
• Packet forwarding
• Packet validation, address parsing, table lookup,
  time-to-live (TTL) control, checksum calculation
• Special services
• Packet encapsulation, authentication, traffic
  management

6
Bus-based router arch. w/ single CPU

• First generation router
• Software implementation on a single CPU
• Shared bus

7
Bus-based(cont.)

• Major system bottleneck centralized data memory
• Low performance due to
• All packets have to be processed by the central
  CPU
• Memory intensive operations (such as table
  lookup) limit the effectiveness of the processor
  power upgrade
• Moving data from one interface to another is a
  time-consuming task
• It does not scale well for multigigabit interfaces

8
Bus-based arch. w/ multiple CPUs

• Architecture with route caching
• Second generation IP routers, use caching to
  reduce the load on the system bus

9
Architectures w/ multiple forwarding engines

• Multiple forwarding engines are connected in
  parallel to achieve high packet processing rates

10
Switch-based arch. w/ multiple CPUs

• Third generation routers shared bus replaced by
  a switch fabric
• Throughput is increased several orders of
  magnitude

11
Switch-based routers w/ fully distributed
processors

• Preceding architectures have three main
  bottlenecks
• Processing power add processing power to network
  interfaces (NI)
• Memory bandwidth add some memory to NIs
• Internal bus bandwidth replace with a switch

12
A high level functional diagram for a distributed
router architecture
13
Forwarding table structure
14
IP packet processing

• IP header validation
• Route lookup and header processing
• Packet classification
• Forwarding engine functions (e.g., drop,
  accounting)
• System controller is informed about the new
  packet
• System controller reserves a memory location for
  new packet
• Egress ports are signaled
• Egress port extracts packet from shared memory
  (queuing algor.)
• Egress port notifies the system controller about
  the departure of the packet and memory location
  is made available for new packet