System Design and Implementation with SPW

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System Design and Implementation with SPW

• PRESENTED BY Tapan Kapoor
• Date - 25th August 2003

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Agenda

• Overview
• System Design untimed functional
• Fixed-point exploration
• Implementation

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Design Activities
Modeling


Verification
Optimization


Representation
Visualization
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Need for System Level Design

• design complexity
• time to market

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System Level Design

• System-on-Chip (SOC) Design
• Increase of Design Complexity
• Move to higher levels of Abstraction

Level
Number of Components
System Level
ALGORITHM RTL GATE TRANSISTOR
1E0
Abstraction
Accuracy
1E1
1E2
1E3
1E4
1E5
1E6
1E7
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Algorithmic Design Challenges Cellular Evolution
3G
3GPP CDMA2000

• Hybrid ARQ protocol
• Turbo Coding
• 2 Mbps
• Transmit Diversity
• Multiple channels
• Multiple symbol rates
• Multiple modulation schemes

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Algorithmic Design Challenges Design Complexity

• CDMA2K example, one of 16 modes
• Physical layer standard is gt500 pages
• How do you know your tests are complete and
  correct?

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Algorithmic Design Challenges Analog/RF Modeling

• Peak to average power ratio no longer 1
• Nonlinearities, phase jitter, noise figure
  important to overall system performance
• UWB systems will have a 3-10 GHz bandwidth
• Analog/RF models must be very fast.

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Algorithmic Design Challenges Control Modeling

• Hybrid ARQ schemes require tight MAC and PHY
  integration
• Need to model both MAC PHY for performance
  tests (system throughput).
• Modeling of bus interfaces
• Design of the higher protocols
• Verification of the software

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System DesignAbstraction Levels
Structural/ Implementation Detail
Order/ Timing Detail
System Design
Untimed (causality)
Functional
Timed (estimated)
Structural
Bus- Functional
Timing- accurate
Cycle- accurate
RTL/ISS
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Design and Verification
design at various levels
enables
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Algorithm Design Flow

• Datapath intensive design flow
• Consistent capture method for testbench and
  design
• Model design and environment
• Floating point model is the FVP

Floating Point Algorithm
Fixed Point Algorithm
Consistent Testbench
Hardware/Software Design FGPA, ASIC or DSP RTL,
SystemC, C, Asm
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Design Flow Algorithms to Hw
Capture algorithm (Specification)
Floating-Point Algorithm
Verify algorithm, refine types, decide bit-widths
Fixed-Point Algorithm

• Test Bench
• (Stimulus and Simulation models)

Define architecture of the design
Fixed Point Architectural Design
Verify algorithms hardware implementation
RTL to Gate-level Translation
Physical Design (Place and Route)
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Algorithm Design and Verification

• Hierarchical Capture
• Signal Analysis
• Mixed-level Verification
• Optimal Implementation

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Dataflow Design and Platform FVP
Dataflow design
Datapath HW IP
Application Libraries
Environment Models
DSP SW IP
Analog /RF Behavior
DSP
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Granularity of Communication

• Token Level (Dataflow Tokens)
• Transaction Level (Bus Read/Write)
• Signal Level (Bits and Bitvectors)

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Transaction Level Modeling TLM
Transactions
Signals
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Unified Verification Methodology FVP Concept
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Functional Virtual Prototype FVP
B2
B1
B3
B4

• Processor Software

• Digital RTL

• Analog/Mixed Signal

• Dataflow/DSP

• Transaction-Level Model

• Block Implement. and Test

• Block Verification In System

• Block Integration, System Verification

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System design in SPW
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HW implementation in SPW
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Example Design
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Demonstration

• System design behavioral IDCT design
• Fixed-point exploration
• Implementation Cycle accurate IDCT