Deuterium Implantation In Si/SiO2 Interface

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Deuterium Implantation In Si/SiO2 Interface

• Presented
• By,
• Amrita
  Banerjee
• 01.31.05

2
Introduction

• Reliability of Si/SiO2 interface in MOS
  transistors remained the focus of mainstream
  research for a long time.
• Problem with Dangling Bonds
• Leakage current at the Si/SiO2 interface.
• Reduced channel conductance.
• Deviation from the ideal Capacitance- voltage
  characteristics.
• In 1971 Nicollian et.al. used H2 to passivate the
  dangling bonds

Ref D. Misra , R.K.
Jarwal, Journal of The Electrochemical Society,
149 (8), 2002.
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Use of Hydrogen in the Interface

• Passivates the Dangling Bonds at the Si/SiO2
  interface.
• Pb H2 PbH
  H
• Hence it reduces the interface trap charge
  density and improves the stability of the device.
• Reduces the leakage Current.
• Improves the Threshold Voltage distribution
  and the Transconductance significantly with
  respect to a reference device (control).
• - In an untreated
  wafer, the mean and variation of the threshold
  voltage and the transconductance are very high,
  which is beyond the acceptance level.

Ref D. Misra , R.K. Jarwal, Journal of The
Electrochemical Society, 149 (8), 2002.
A.H. Nicollian et al, J. Appl.
Phys. 42, 1971
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The Problem unsolved by Hydrogen

• Further a time-dependent degradation of metal
  oxide semiconductor ( MOS) transistor performance
  results due to the hot electron effects.
• Hot electrons stimulate the desorption of
  hydrogen from Si/SiO2 interface region.
• Ref J.W. Lynding et al. Appl. Phys. Lett. 68
  (18), 29 April 1996.
• S.N Rashkeev et al. Phys. Rev Lett.
  87(16), 15 October 2001.
• 
  
  

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The advent of Deuterium

• It has been proven that Deuterium implication is
  much more efficient than that of traditional
  Hydrogen.
• Deuterium is much more difficult to remove under
  the condition used to desorb Hydrogen due to the
  additional neutron mass.
• It improves the Transconductance distribution
  compared to hydrogen.
• Transistor life time increases by a factor of 10-
  50.
• It also improves the threshold voltage.
• It is suitable for integrated circuits and
  multilevel dielectric and metallization layers.
• Ref J.W. Lynding et al. Appl. Phys. Lett. 68
  (18), 29 April 1996.
• R.A. B. Devine et al. Appl. Phys. Lett. 70
  (22), 2 June 1997.

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Graphical comparison between D2 and H2 annealed
devices.

• Expression for, Threshold Voltage Shift,
• ? Vt (q/ Cox) d Nit
• Where, d Nit Number density of
  interface states averaged over the channel
  length.
• Cox Gate oxide
  capacitance
• q electronic
  charge.
• Expression for channel transconductance
  degradation
• ?Gm a d Nit/ (1 a d Nit) Gmo
• Where, Gmo Ungraded channel
• 
  transconductance.
• a processing
  related parameter.
• Vt can be written in terms of ?Gm , which
  is-
• ? Vt (q/ Cox) ?Gm /Gmo 1- ?Gm
  /Gmo

The channel transconductance measured in a 0.25
mm MOSFET subjected to hot-electron stressing.
The source-drain voltage was 3.5 V and the
substrate current, 0.14 mA. h! hydrogen annealed
devices, l! deuterium annealed devices.
Ref R.A.B. Devine et al. Appl Phys. Lett. 70
(22), 2 June 1997.
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Contd.
8
Contd.
Ref J.W. Lynding et al. Appl. Phys. Lett. 68
(18), 29 April 1996.
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Contd.

• The degradation of gate induced drain leakage (
  GIDL) current under hot- carrier stress was
  studied in n- channel MOSFETs that were annealed
  in Hydrogen and deuterium and then compared.

Ref Kangguo Cheng et al. IEEE ELECTRON DEVICE
LETTERS, VOL. 24, NO. 7, JULY 2003
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Analytical Model to project MOS lifetime
improvement by Deuterium Passivation of interface
traps.

• It is a universal model by which the device
  lifetime improvement due to deuteration can be
  projected.
• ?NitH(t) -?NitM(t) CD ?NitH(t)
  -?NitD(t)
• Where, ?NitH(t), ?NitM(t), ?NitD(t) are
  the interface trap generation at given tress
  time, t.
• Interface trap generation under hot- carrier
  stress can be described by the power law,
• ?Nit (t) Atn A fitting parameter.
• Depending on the above relation the first
  equation can be written as,
• (AHtn AMtn) CD (AHtn ADtn)
• or,
• AM AH CD(AD - AH) these are
  prefactors of the transistors.
• Therefore, the life time improvement factor
  (IMP),
• tM/tH ?NitM(t)/ AM1/n/
  ?NitH(t)/ AH1/n AH /AM 1/n

Ref IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO.
10, OCTOBER 2003
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Electrical and Physical Characterization of
Deuterium sinter

• Comparing the impact of deuterium sinter (under
  two different annealing condition, 4500C/60min,
  4500C/90min) with the traditional Forming Gas
  (FG) sinter over a NMOS transistor, it is seen
  that D2 sinter at 60 min increases the life time
  10 times over the FG sinter.

CHC lifetime based upon 10 change in gm for
NMOS devices annealed in FG and D2 for
two different sinter times.
Ref A.G.Mogul et al. Appl. Phys. Lett. 72 (14),
6 April 1998.
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Contd.

• High pressure deuterium annealing reduces the
  annealing time and increases the life time as
  well.
• It shows, for example, annealed at 6
  atm. for 1h annealed at 2 atm. for 3h.
• Ref Jinju Lee et al. IEEE ELECTRON DEVICE
  LETTERS, VOL. 21, NO. 5, MAY 2000

hot electron degradation lifetime versus
substrate current for these devices which come
from wafers having four metal layers with nitride
sidewalls and SiON capping layer
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Reliability of thin oxide grown on Deuterium
implanted silicon substrate

• In that case deuterium incorporated at Si/SiO2
  interface before the application of gate oxide.
• It was done through a low energy ion implantation
  into Si substrate.
• This process was done at a dose of 1X1014/cm2 at
  25 keV.
• It showed a improved charge- to- breakdown
  characteristics.
• Ref D Misra and R.K. Jarwal. IEEE TRANSACTION ON
  ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001

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Results

• It was observed through the conductance method
  that Dit or Nit is much smaller (at 25 KeV) than
  compared to the other cases.
• Reduction of Dit improves the charge-to-
  break characteristics.

Ref D Misra and R.K. Jarwal. IEEE TRANSACTION ON
ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001
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Results
Ref D Misra and R.K. Jarwal. IEEE TRANSACTION ON
ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001
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Interface Hardening with Deuterium Implantation

• It is now known that hot carrier degradation in
  MOS transistors has a great impact on threshold
  voltage instability, transconductance
  degradation.
• The generation of interface trap charge is due to
  hot carrier stimulated hydrogen desorption and
  silicon dangling bond passivation.
• Replacing hydrogen with deuterium has the same
  impact but it is more advantageous.
• As chemical properties of Hydrogen and deuterium
  are virtually almost same, so there occurs no
  basic changes in the experiment as well.
• It was also examined that if nitrogen is
  implanted into the Si substrate at low - energy
  and after that the deuterium is implanted into
  that substrate ( by ion implantation process)
  before gate oxide formation, then the oxide
  reliability increases.
• Deuterium implantation has a uniform distribution
  where as diffusion has a localized effect due to
  side- wall spacers.

Ref D.Misra and R.K. Jarwal, Journal of the
Electrochemical Society, 149(8), 2002 DMisra et
al, Electrochem. Solid- state Lett. 15,
460,1999.
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Results
Given figure shows that implanted deuterium
partially neutralizes the oxide/ interface
charge. It is also clear that deuterium implanted
at 25KeV shows the maximum Si/SiO2 interface
charge passivation.
Figure 1. The flatband voltage shifts and net
oxide charge extracted from high-frequency C-V
measurements for various deuterium implanted
samples.
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Contd.
Representation of possible deuterium diffusion
The figure shows that interface passivation
depends on the implantation condition.
Figure 2. Schematic representation of possible
deuterium diffusion in silicon for various
implantation conditions shows that deuterium
might have out-diffused for 15 keV implantation
and never reached the interface for 35 keV
implantation during gate oxide growth.
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Contd.
The average values of initial electron trapping
slopes (IETS) for25KeV implanted devices are
shown in this figure.
Figure 3. The average values of the initial
electron trapping slope for the 25 keV
deuterium-implanted samples when compared to
control device. Initial oxide trap creation was
suppressed for deuterium-implanted sample.
20
Contd.
(a) Measured conductance at 1 MHz as a function
of gate voltage for various samples and (b)
conductance peak for 25 keV implanted sample at
two different frequencies.
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Results
Figure 5. Peak Nit values for different deuterium
implantation conditions indicate that Nit went
through a minimum value (for 25 keV implantation)
as a function of implantation energy.
Figure 6. Density of interface traps Dit as
obtained from the conductance measurements. The
trap energy ET is with respect to intrinsic Fermi
level EI
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Advantages

• Deuterium atoms incorporated at 25 KeV, not only
  passivate the danling bonds and forms Si- D bonds
  at the Si/SiO2 interface, but also forms the Si-
  D bonds at bulk SiO2.
• Deuterium implantation before gate oxide
  application is an effective way to improve the
  oxide quality by interface hardening.
• Previously described process takes less time
  than that of the annealing through traditional
  back- end process.
• Reduction of oxide charge due to deuterium atoms
  implications indicates the improvement of gate
  oxide quality.
• Compared to FG annealing, Deuterium annealing
  gives better threshold voltage stability and
  reliability characteristics even to the hafnium
  oxide gate dielectric MOSFET under high voltage
  stress.

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Drawback

• It was observed that Negative Bias Temperature
  Instability (NBTI) is accelerated by
  high-pressure hydrogen or deuterium annealing
  compared to FG annealing. It not only causes
  higher density of oxide charges but also causes
  interface defect.

Ref Jae Sung Lee et al. IEEE ELECTRON DEVICE
LETTERS, 2004.
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Application

• The effects of low- temperature deuterium
  annealing on the reduction of dark currents in
  the CMOS active pixel sensor ( APS) have been
  investigation.
• It is also found that dark currents generated
  from the photo diode, transfer gate and floating
  diffusion node region can be reduced more by
  using deuterium annealing process.
• It is observed that there occurs a significant
  reduction of hot- carrier- induced 1/f (flicker)
  noise of MOS transistors using deuterium anneal
  over traditional hydrogen anneal.

Ref Hyuck In Kwon et al. IEEE Transactions on
Electron devices. Vol. 51. No.8, Aug. 2004.
Zhi Chen et al. IEEE Electron Dev. Lett., 2003.
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Summery

• Problem with dangling bonds.
• Interface trap charge passivation by H2.
• Comparison of D2 and H2 annealed device
  characteristics.
• Properties of Deuterium implantation at the
  interface.
• Deuterium implantation before gate oxide growth
  and its result.
• Interface hardening with deuterium implantation
  and its results.

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• Thank You