ECE 501

1
ECE 501

• Session 7
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

2
Counters

• Binary up/down counter
• Inputs
• Inc
• Dec
• Data
• Clock
• load
• Outputs
• Count
• Behavior
• If inc is true, count count 1 on clock edge
• If dec is true, count count 1 on clock edge
• If ld is true, count data on clock edge
• If inc and dec are true, count count
• Load takes priority over count

3
Binary Up/Down Counter
data
load
inc
dec
clock
count
4
Verilog for up/down counter
//up_down_counter.v //parameterized binary
up/down counter module up_down_counter(COUNT,clk,i
nc,dec,load,DATA) parameter width 4 output
width-10 COUNT input width-10
DATA input clk, inc,dec,load reg
width-10COUNT always _at_(posedge clk) if
(load) COUNT lt DATA else if (inc dec)
COUNT lt COUNT else if
(inc) COUNT lt COUNT 1 else if (dec) COUNT
lt COUNT -1 else COUNT lt COUNT endmodule
5
Simulation Results
6
More Counter Types

• Ring Counter
• Circular shift register with only one bit set
• BCD (Binary Coded Decimal)
• Counts from 0000 to 1001. Next count after 1001
  is 0000
• Modulo N counter
• Counts from zero to N-1. (e.g. BCD is modulo 10
  counter)
• Johnson Counter

7
Verilog Example Modulo N Counter
//mod_count.v //a modulo N counter example module
mod_count(count, N, clk) parameter
width16 output width-10count input
width-10N //the actual width of N is log2
(N) input clk reg width-10count always
_at_(posedge clk) if (count lt N-1) count lt count
1 else if (count N-1) count lt 0 endmodule
8
Simulation ResultsModulo 3 Counter
9
Separating Data Path and Control

• Design Guidelines Suggest Separating Data Path
  and Control
• One Approach
• Use Combinatorial Logic for Data Path Functions
• Use Sequential (State Machine) Logic for Control
• Integrate with top level module
• Connects pieces together

10
A Partial Computer
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Building Blocks for our Partial Computer

• Memory
• Registers
• Memory Address Register (MA)
• Memory Data Register (MD)
• Instruction Register (IR)
• Register/Counter
• Program Counter (PC)
• Control Unit
• FSM that issues all control signals

12
Memory
module mem ( address, we, outenab, dio) inp
ut 70 address input we input
outenab inout 70 dio lpm_ram_io lpm_ram_io
_component ( .dio (dio), .outenab
(outenab), .address (address), .we
(we)) defparam lpm_ram_io_component.intended_d
evice_family "UNUSED", lpm_ram_io_component.lp
m_width 8, lpm_ram_io_component.lpm_widthad
8, lpm_ram_io_component.lpm_indata
"UNREGISTERED", lpm_ram_io_component.lpm_address
_control "UNREGISTERED", lpm_ram_io_component.
lpm_outdata "UNREGISTERED", lpm_ram_io_compone
nt.lpm_file "mem_test.mif", lpm_ram_io_compone
nt.use_eab "ON", lpm_ram_io_component.lpm_type
"LPM_RAM_DQ" endmodule

• Use the Altera Wizard to Generate Memory Module

13
Register

• Create a Module to be used as a Register
  (multiple instances)

//greg.v //A general register used in the
machine module greg(X, ld, clk,Y) parameter
width8 input width-10 X input ld,
clk output width-10 Y reg width-10
Y always _at_(posedge clk) if (ld) Ywidth-10
lt Xwidth-10 endmodule
14
Register/Counter

• Create a Register/Counter Module for the Program
  Counter

//reg_counter.v //A register counter used for the
program counter module reg_counter(X, ld, clk,
inc,Y) parameter width8, increment1 input
width-10 X input ld, clk, inc output
width-10 Y reg width-10 Y always
_at_(posedge clk) if (ld) Ywidth-10 lt
Xwidth-10 else if (inc
!ld) Ywidth-10 lt Ywidth-10
increment endmodule
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Control Unit

• Generate Control Signals and Manage Timing

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Putting it Together

• Now that we have defined all of the building
  blocks, how do we put them together
• This examples integrates many of the items
  discussed earlier
• Refer to the following chart to map the Verilog
  to our problem

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Putting it Together (cont)
18
Putting it Together (cont)
19
Memory Initialization
20
Initial Simulation (Clock Period 100 ns)
21
Simulation (Clock Period 20 ns)
22
Simulation (Clock Period 10 ns)
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Summary

• Design examples provide fundamental tools needed
  to implement a design.
• Organizing design files can make job easier
• Use Separate Directories e.g.
• SRC - CPU
• - RAM
• - register
• - register-counter
• My top level directory for this effort was SRC
  (contains only folders)
• Separate projects were developed for the Memory
  (RAM), register (g_reg), and the register-counter
  (reg_count)
• The main project is located in the CPU folder and
  is called CPU
• When building the CPU project, add the other
  required files to the project but leave them in
  their respective folders

24
Extending the Example

• The above example provided a partial computer
  control unit
• Instructions were fetched sequentially from
  memory but nothing was done with them.
• Lets continue with this example to illustrate a
  prototype instruction decoder process.
• Let the operation code be contained in the first
  three bits of the instruction register.
• Expand the state table to include an additional
  eight states to correspond to the eight possible
  instructions
• Use the decoder output to generate the next state
  for the state machine

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Extended RTL
     
26
Extended Fetch (Includes Decoder Prototype)
27
Simulation
28
Serial Data Transmission

• RS- 232
• Standard Serial Ports for PC
• Interfaces based on devices called UARTs
• Universal Asynchronous Receiver Transmitter
• Asynchronous Communication
• Each character sent asynchronously
• Receiver must detect the beginning and end of
  each character
• Rates are relatively slow (300, 600, 1200, 2400,
  4800, 9600, 14400, 28800, etc.)
• Reference page 378 in text
• Read for next time

29
Signal Definition

• Start Bit
• High for one bit time
• Data Bits
• Transmitted LSB first
• Characters usually transmitted in 7-bit ASCII
  format
• Eighth data bit is a parity bit
• Stop Bit
• Low for at least one bit time
• Rest State
• State of signal between characters
• Low

30
PC Comm Port Signal Levels

• Voltage Levels are 12.5 V and 12.5 V
• Rest State is 12.5 V
• Logic 1 is 12.5 V
• Logic 0 is 12.5 V

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UART Receiver Architecture
32
Example Receiver Design

• Page 394 in Text
• Assumes that sample clock is 8 times the
  frequency of the bit clock
• Typical differences are an order of magnitude
  more
• Implies that start bit sample size is four

33
Example Receiver Verilog Code
// uart_rcvr.v // An 8-bit uart receiver module
based on Ciletti module uart_rcvr (RCV_datareg,
read_not_ready_out,Error1, Error2, Serial_in,
read_not_ready_in, Sample_clk, reset_) //sample
clock is 8 times bit clock (Bit_clk) parameter wor
d_size 8 parameter half_word
word_size/2 parameter Num_counter_bits 4 //mus
t hold count of word_size parameter Num_state_bits
2 //Number of bits in state parameter idle 2
'b00 //Encode idle state parameter starting 2'
b01 //Encode starting state parameter receiving
2'b10 //Encode receiving state   output word_
size-10 RCV_datareg //Declare
outputs output read_not_ready_out, Error1,
Error2 input Serial_in, //Declare
inputs Sample_clk, reset_, read_not_ready_in
reg inc_Bit_counter, //Declare all one-bit
registers clr_Bit_counter, inc_Sample_counter,
clr_Sample_counter, shift, load, read_not_ready
_out, Error1, Error2   reg word_size-10 RCV_
datareg, RCV_shiftreg reg Num_counter_bits-1
0 Sample_counter //Works for the 81
relationship // between sample clock and
bit clock reg Num_counter_bits0 Bit_counter r
eg Num_state_bits-10 state, next_state
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Example Verilog UART Receiver (Cont)
//Combinatorial logic for next state and
conditional outputs always _at_(state or Serial_in
or read_not_ready_in or Sample_counter or
Bit_counter) begin read_not_ready_out
0 inc_Bit_counter 0 clr_Bit_counter
0 inc_Sample_counter 0 clr_Sample_counter
0 shift 0 load 0 Error1
0 Error2 0 next_state state
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Example Verilog UART Receiver (Cont)
case (state) idle if (Serial_in 0)
next_state starting //detects the start
bit starting if (Serial_in
1) begin next_state idle clr_Samp
le_counter 1 end else if
(Sample_counter half_word -1) // counts
samples equal to ½ word time begin next
_state receiving clr_Sample_counter
1 end else inc_Sample_counter
1 receiving if (Sample_counter lt
word_size -1) //counts samples equal to one word
time inc_Sample_counter 1 else beg
in clr_Sample_counter 1 if
(Bit_counter ! word_size) begin sh
ift 1 inc_Bit_counter
1 end else begin next_stat
e idle read_not_ready_out
1 clr_Bit_counter 1 if
(read_not_ready_in 1) Error1
1 else if (Serial_in 0) Error2
1 else load 1 end end
default next_state idle endcase end
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Example Verilog UART Receiver (Cont)
//state transitions and register
transfers always _at_(posedge Sample_clk) begin
if (reset_ 0) begin state lt
idle Sample_counter lt 0 Bit_counter
lt 0 RCV_datareg lt 0 RCV_shiftreg lt
0 end else begin state lt
next_state if (clr_Sample_counter
1) Sample_counter lt 0 else if
(inc_Sample_counter 1) Sample_counter lt
Sample_counter 1 if (clr_Bit_counter
1) Bit_counter lt 0 else if
(inc_Bit_counter 1) Bit_counter lt Bit_counter
1 if (shift 1) RCV_shiftreg
lt Serial_in, RCV_shiftregword_size -
11 if (load 1) RCV_datareg
lt RCV_shiftreg end end endmodule
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Simulation Results
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Simulation Results
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UART Transmitter
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Data In Module
//XMT_DATA.V //input data register for
UART module XMT_DATA (data_in, clk, ldxmt,
XMTDATA) input 70 data_in input clk,
ldxmt output 70 XMTDATA reg 70
XMTDATA always _at_(negedge clk) if (ldxmt)
XMTDATA lt data_in endmodule
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Transmitter Shift Register Module
//xmt_shift.v //shift register for serial
transmission module xmt_shift (data_in, clk, ld,
shift, clear, serial_out) input 70
data_in input clk, ld, shift, clear output
serial_out reg 90 XMT reg
serial_out always _at_(negedge clk or negedge
clear) if (!clear) begin XMT lt 10 'b
1111111111 serial_out lt XMT0 end els
e if (ld ) XMT lt 1'b1, data_in,
1'b0 else if (shift) XMT, serial_out
lt 1'b1, XMT else XMTltXMT endmodule
42
Bit Count Module
//BitCount.v //register to count bits as they are
transmitted module BitCount(clk, inc, clear,
eq9) input clk, inc, clear output eq9 reg
30 COUNT reg eq9 always _at_(posedge clk or
negedge clear) if (!clear) begin eq9 lt 0
COUNT lt 0end else if (inc) begin
if (COUNT lt 8) begin COUNT lt COUNT 1eq9
lt 0end else if (COUNT 8) begin
COUNT lt 0 eq9 lt 1end else if (COUNT gt 8)
begin COUNT lt 0 eq9 lt 0end
end endmodule
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Controller Module
//cntl.v //controller for UART TRANSMITTER module
cntl (byte_ready, eq9, reset, T_byte, inc,start,
shift, clear, ldxmt, ldXMT_shift, clk) input
byte_ready, eq9, clk, reset, T_byte output inc,
start, shift, clear, ldxmt, ldXMT_shift reg
ld_xmt, start, shift, clear1, inc, ldxmt,
ldXMT_shift reg 10 state always _at_(posedge
clk or negedge reset) begin clear
1'b1 if (!reset) begin state lt
0 clear lt reset end
else case (state) 0 if
(byte_ready) begin ldxmt lt 1'b1 clear lt 1
state lt 1 end else state lt 0
1 begin ldXMT_shift lt 1'b1 ldxmt lt 1'b0
state lt2 end 2 begin
ldXMT_shift lt 1'b0 if (T_byte)

begin
start lt 1 state lt 3 end else state lt
2

end
3 if (!eq9) begin shift lt1 inc lt 1 start lt
0 state lt 3 end else begin inc lt 0
shift lt 0 clear lt 0 state lt 0 end
endcase end endmodule
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Top Level Module
//uartxmt.v //toplevel file for uart xmtr module
uartxmt (datain, byte_ready, T_byte, clk, reset,
serial_out, ld, ldxmt, clear, data) input 70
datain input byte_ready, T_byte, clk,
reset output serial_out, ld, ldxmt,
clear output 70 data //for
instrumentation //instantiate
modules XMT_DATA xmtdatain (datain, clk, ldxmt,
data) xmt_shift xmtshift (data, clk, ld, shift,
clear, serial_out) BitCount count (clk, inc,
clear, eq9) cntl controller (byte_ready, eq9,
reset, T_byte, inc, start, shift, clear, ldxmt,
ld, clk) endmodule
45
Simulation
Controller Delay between Bits (Latency)
46
Example Problems

• Approximately three bit-time delay between end of
  stop bit and next start bit
• Part of problem due to mechanizing interface
  register with the transmission controller
  (introduces an extra clock)
• Other delays due to controller design and module
  design
• e.g. State machine mechanization is straight
  forward but not optimum
• Optimizing state machine can easily eliminate
  two-bit times of delay

47
Clock Generator

• Need a variable clock for the transmitter and
  receiver
• Consider developing a module that does the
  following
• INPUT
• system clock
• output frequency selection
• OUTPUT
• Transmitter
• Bit Rate Clock
• Receiver
• Bit Rate Clock
• Sampling Clock

48
Strategy
Table supports counts for ½ the period of the
respective clock.
Count 3 edges of system clock and transition
49
Partial Verilog
always _at_(posedge sys_clock) begin if
(s_count 0) begin sample_clock
!sample_clock s_count sample_count end else
s_count s_count -1 if (b_count 0) begin
bit_clock !bit_clock b_count bit_count
end else b_count b_count -1 end
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Sample Timing
System Clock 5 MHz Bit Clock 115 Kbps
51
Serial Port Test Software

• Computers in 351G and 302 have a suite of test
  software which allow you to send characters to
  the serial port.
• WINCOMM is the most flexible since it allows
  selection of the bit rate from a drop down menu
  and allows character entry in a dialog box.
• Other programs provide fixed bit rate and run in
  a console window.
• Use this to send characters to your project boards

52
Hardware Issues

• You must construct a level shifter or obtain a
  level shifter for the FPGA reduce the RS-232
  12.5 V to 0 5 V. The device will be destroyed
  if this is not done. The boards you will use
  have a level shifter circuit connected to the
  DB-9 connector.
• Us the logic analyzers in 351 G to monitor your
  hardware. Bring out some of the internal signals
  for instrumentation purposes. (Beware of pin
  limitations)