Design for Manufacturability

1
Design for Manufacturability

• Prof. David Pan
• dpan_at_ece.utexas.edu
• Office ACES 5.434

Thanks to Warren Grobman, Andrew Kahng
2
Outline

• Manufacturability Basics
• OPC, Composability
• Performance Impact Limited Fill Insertion
• Redundant vias CMP
• Futures of Mfg-Aware PD

3
Photo-Lithographic Process
optical
mask
oxidation
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
4
Lithography systems
5
Lithography Primer Basics

• The famous Raleigh Equation
• ? Wavelength of the exposure system
• NA Numerical Aperture (sine of the capture angle
  of the lens, and is a measure of the size of the
  lens system)
• k1 process dependent adjustment factor
• Exposure the amount of light or other radiant
  energy received per unit area of sensitized
  material.
• Depth of Focus (DOF) a deviation from a defined
  reference plane wherein the required resolution
  for photolithography is still achievable.
• Process Window Exposure Latitude vs. DOF plot
  for given CD tolerance

6
Numerical Aperture

• NAnsin? ? nrefractive index ? for air, UB 1.
  Practical limit 0.93
• NA increase ? DOF decrease
• Immersion lithography ? ? ngt1 (e.g., water)

Figures courtesy www.icknowledge.com
7
k1

• k1 is complex process depending on RET
  techniques, photoresist performance, etc
• Practical lower limit 0.25
• Minimum resolvable dimension with 193nm steppers
  0.25193/0.93 52nm

Source www.icknowledge.com
8
Mask versus Printing
Figures courtesy Synopsys Inc.
9
Data Volume Explosion
Number of design rules per process node
MEBES file size for one critical layer vs.
technology node
10
RET Layers Explosion
Number of TSMC Mask Layers Using OPC/PSM
Number of design rules per process node
0
180nm
150nm
130nm
90 nm
Source TSMC Technology Symposium, April 22 2003
11
Design Rules Explosion
Number of design rules per process node
12
Variation Across-Wafer Frequency
13
Process Variation Taxonomy

• Spatial scale
• Die-to-Die or Inter-Die. E.g. Focus, etch
• Within-Die or Intra-Die. E.g. lens aberration,
  diffraction effects
• Nature
• Random. E.g. batch-to-match material variation
• Systematic. E.g. diffraction-based proximity
  effects
• Systematic but difficult to model variations ?
  random

14
Process Variation Sources

• Wafer topography, reflectivity
• Reticle CD error, proximity effects, defects
• Stepper Lens heating, focus, dose, lens
  aberrations
• Etch Power, pressure, flow rate
• Resist Thickness, refractive index
• Develop Time, temperature, rinse
• Environment Humidity, pressure

15
RET Basics

• The light interacting with the mask is a wave
• Any wave has certain fundamental properties
• Wavelength (?)
• Direction
• Amplitude
• Phase
• RET is wavefront engineering to enhance
  lithographyby controlling these properties

Direction
Amplitude
Phase
Courtesy F. Schellenberg, Mentor Graphics Corp.
16
Direction Illumination

• Regular Illumination
• Many off-axis designs (OAI)
• Annular
• Quadrupole / Quasar
• Dipole

17
OAI Impact on PD

• Off axis amplifies certain pitches at the expense
  of the others ?Forbidden pitches
• Quasar / Quadrupole Illumination
• Amplifies dense 0, 90 lines
• Destroys 45 lines
• Dipole Illumination
• Prints only one orientation
• Must decompose layout for 2 exposures

Depth of Focus
Pitch (nm)
Graph reference Socha et al. Forbidden Pitches
for 130 nm lithography and below, in Optical
Microlithography XIII, Proc. SPIE Vol. 4000
(2000), 1140-1155.
18
Amplitude OPC

• Optical Proximity Correction (OPC)modifies
  layout to compensate for process distortions
• Add non-electrical structures to layout to
  control diffraction of light
• Rule-based or model-based

19
OPC Assist Features
Process Overlap Window
Iso-window after SRAF insertion

• SRAF Sub-Resolution Assist Feature
  SB Scattering Bar
  Assists
• SRAFs make isolated lines behave as dense
• SRAF are not supposed to be printed on wafer but
  exist on mask

20
Function-Aware OPC

• Annotate features with required amount of OPC
• E.g., why correct dummy fill?
• Determined by design properties such as setup and
  hold timing slacks, parametric yield criticality
  of devices and features
• Reduce total OPC inserted (e.g., SRAF usage)
• Decreased physical verification runtime, data
  volume
• Decreased mask cost resulting from fewer features
• Supported in data formats (OASIS, IBM GL-I,
  OA/UDM)
• Design through mask tools need to make, use
  annotations
• N.B. General RET trajectory rules ? models ?
  libraries

21
OPC and Designers Intent

• OPC applied post-tapeout
• Overcorrection (matching corners) ? mask cost
• Large runtimes
• Impact of OPC on performance unknown
• Designers intent OPC quality metrics
• CD (Poly over active)
• Non-critical poly need
• not be well-controlled
• Contact Coverage
• Perfect corners unnecessary
• if there is enough contact overlap

22
Example Caution OPCing OPC

• Historical rule on line end extension
• OPC software assumes the layout is the target,
  and adds OPC to the old OPC extension
• With model-based OPC, design rules can be much
  more aggressive

Truly desired on wafer
Layout according to design rule
OPC on the OPC
Figures courtesy F. Schellenberg, Mentor Graphics
Corp.
23
Phase PSM

• Phase Shifting Masks (PSM) etch topography into
  mask
• Creates interference fringes on the wafer
  ?Interference effects boost contrast ?Phase Masks
  can make extremely small gates

phase shifting mask
conventional mask
glass
Chrome
Electric field at mask
Intensity at wafer
24
Phase-Shifting
Mask

• Uses phase-modulation at the mask level to
  further the resolution capabilities of optical
  lithography
• Benefits
• Smaller feature sizes
• Improved yield (process latitude)
• Dramatically extends useful life of current
  equipment
• Performance Boost
• Chip Area/Cost Advantage
  for Embedded Systems
• Modified Architecture Based on Higher Speed Busses

Printed using a 0.18 mm nominal process
Figure Courtesy of Numerical Technologies, Inc.
25
The Phase Assignment Problem

• Assign 0, 180 phase regions such that critical
  features with width lt B are induced by adjacent
  phase regions with opposite phases

0
180
ltB
26
Key Global 2-Colorability

• Odd cycle of phase implications layout
  cannot be manufactured
• layout verification becomes a global, not local,
  issue

?
180
0
180
0
180
180
27
Phase Assignment for Bright-Field PSM

• PROPER Phase Assignment
• Opposite phases for opposite shifters
• Same phase for overlapping shifters

Overlapping shifters
28
Critical features F1,F2,F3,F4
F2
F4
F1
F3
29
F2
F4
F1
F3
Opposite-Phase Shifters (0,180)
30
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Shifters S1-S8

• PROPER Phase
  Assignment
• Opposite phases for opposite shifters
• Same phase for overlapping shifters

31
Phase Conflict
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Phase Conflict
Proper Phase Assignment is IMPOSSIBLE
32
Conflict Resolution Shifting
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Phase Conflict
feature shifting to remove overlap
33
Conflict Resolution Widening
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
Phase Conflict
feature widening to turn conflict into
non-conflict
34
Minimum Perturbation Problem

• Layout modifications
• feature shifting
• feature widening
• ? area increase, slowing down
• ? manual fixing, design cost increase

• Minimum Perturbation Problem Find min of
  layout modifications leading to proper phase
  assignment. Kahng et al. ASPDAC 2001

35
Conflict Graph for Cell-Based Layouts

• Coarse view at level of connected components of
  conflict graphs within each cell master
• each of these components is independently
  phase-assignable
• can be treated as a single vertex in
  coarse-grain conflict graph

cell master A
cell master B
connected component
edge in coarse-grain conflict graph
36
Standard-Cell PSM

• Must free composability of standard cells
• Exit placer with a phase-shiftable layout
• No loops back into the placer
• RETs may interfere unique master cell with only
  one instantiation causes area loss
• Can exploit
• Multiple phase-shifted versions of master cell
• Version-composability matrix

37
Taxonomy of Composability

• (Same) Same row composability any cell can be
  placed immediately adjacent to any other
• (Adj) Adjacent row composability any two cells
  from adjacent rows are freely combined
• Four cases of cell libraries G guaranteed
  composability NG
  non-guaranteed composability
• Adj-G/Same-G ? free composability
• Adj-G/Same-NG ? less free
• Adj-NG/Same-G ? painful
• Adj-NG/Same-NG ? non-starter

38
Assist Features and Variation
SB Scattering Bar ? SRAF
0.22
0.2
0.18
0.16
CD?
0.14
0.12
0.1
0.08
2 SB
1 SB
W/O SB
DOF?
0.06
0.04
0.0
0.1
0.2
0.3
0.4
0.5
0.6

• SRAFs are dummy geometries
• Improve process window overlap for dense and
  isolated features
• Not supposed to be printed
• Unavoidable for 90nm poly

SB2
No SB
SB1
39
Layout Composability for SRAFs
Better than
? x ?
?xdx?

• Feature spacings are restricted to a small set
• Two components
• Assist-correct library layouts ? Inter-device
  spacing within a standard cells ? Intelligent
  library design
• Assist-correct placement ? space between cells
  needs to be adjusted ? Intelligent whitespace
  management

40
Lithography and RET
k11.0
k10.6
k10.5
k10.4
k10.3
227nm _at_ 0.85NA
136nm
114nm
91nm
68nm
accurate and flexible modeling is key!
The RETsolutions.
(Courtesy ASML)
41
Mask Costs (1)
Design
Mask Cost ? Data Volume OPC, PSM, Fill ?
increased feature complexity ? increased mask cost
Figure courtesy Synopsys Inc.
42
Mask Costs (2)
Half of all mask sets used for lt 570 wafers (lt
100K parts)
Vector scan Write cost proportional to feature
complexity Difficult to inspect, verify masks!
43
CMP Area Fill
Chemical-Mechanical Planarization (CMP) Polishing
pad wear, slurry composition, pad elasticity make
this a very difficult process step
silicon wafer
slurry feeder
wafer carrier
polishing pad
slurry
polishing table
Area fill feature insertion Decreases local
density variation Decreases the ILD thickness
variation after CMP
Post-CMP ILD thickness
Features
Area fill features
44
Density Control Objectives
Objective for Manufacture Min-Var Kahng et
al., TCAD02 minimize window density
variation subject to upper bound on window
density
Objective for Design Min-Fill Wong et al,
DAC00 minimize total amount of added fill
subject to UB on window density variation
45
Tiling and its Impact on PD
The Tiling Problem Given a layout and a CMP
model, determine the location and amount of dummy
features needed to achieve a planarity target,
and then modify the layout accordingly.

• Planarity Target lt-gt PD Resolution Requirement
• Application ILD, STI, and Copper Tiling
• Tiling Effectively Modifies the Physical Design
• Reticle/Die Array on Wafer Level Design
• Mask Inspection Issues (die to die matching)

46
Tiling for ILD (Al Metallurgy)

• Single Material Polish A Linear Model is
  Sufficient
• Cumulative Effect Also Captured by Linear Models

47
Tiling for STI
Nitride Deposition
Etch
Oxide Deposition
CMP
Nitride Strip

• CMP in STI is a Dual-Material Polish
• Non-Linear Solution Required

48
Tiling for Copper CMP

• Tiling and Slotting Both Oxide Erosion and
  Copper Dishing need to be controlled.
• Three Polish Stages Overburden copper removal,
  Barrier removal, and Oxide over polish.
• Planarity Solution - Research Topic

49
Results from Tiling for STI - I
Density and Post-CMP Topography Simulations for a
DSP chip from Motorola
Shape Density
Topography
Original max 284A
Tiled max 150A
50
Results from Tiling for STI - II
Untiled reticle (768A) (unmanufacturable)
Conventional Rule-Based Tiling (702A) (9
uniformity improvement)
Model-Based Tiling (152A) (80 uniformity
improvement)
51
Intra Layer Effects Delay and Cross-talk
Total Capacitance
l1
l5
1.20
No Tile
Grounded or floating tiles
1.00
Float
0.80
Ground
Capacitance (scaled)
0.60
0.40
Signal line
0.20
substrate
0.00
1
3
5
7
9
Signal line spacing (scaled)
Nearest Neighbor Coupling

• Total capacitance increases
• Longer delay
• Coupling to near neighbors decreases
• Smaller cross-talk

1.20
No Tile
1.00
Float
0.80
Ground
Capacitance (scaled)
0.60
0.40
0.20
0.00
1
3
5
7
9
Signal line spacing (scaled)
52
Capacitance and Delay Models

• Interconnect capacitance Overlap Coupling
  Fringe
• Fringe, Overlap require cognizance of multiple
  layers ? Consider fill impact on
  coupling capacitance only
• Elmore delay model ? incremental additivity of
  delay with added parasitic capacitance

• Capacitance between two active lines separated by
  distance d, with m fill features in one column

53
Inter Layer Effects Delay and Cross-talk
Total Capacitance
u_l1
u_l5
Grounded or floating tiles
1.20
No Tile
1.00
Float
0.80
Ground
Capacitance (scaled)
0.60
Signal line
0.40
0.20
substrate
0.00
d_l5
d_l1
1
3
5
7
9
Signal line spacing (scaled)
Coupling to lower line
Coupling to Lower Line

• Smaller changes than intra-layer case.
• Isolated lines are affected more.
• Coupling to lower line is reduced. Floating tile
  distributes coupling to other lines.
• ISPD05 paper

8.00
No Tile
7.00
Float
6.00
Ground
5.00
Capacitance (scaled)
4.00
3.00
2.00
1.00
0.00
1
3
5
7
9
Signal line spacing (scaled)
54
Effect of Tile Size

• Smaller tiles reduce cross-talk to distant
  neighbors and lead to a smaller increase intotal
  capacitance.

Floating tiles
Signal line
Total capacitance
1.20
No tile
1.00
BUT A small effect next to an analog
component may exceed circuit
spec Circuit Constraints can Be Essential
1x width/space
2x width/space
0.80
Full cover
Capacitance (scaled)
0.60
0.40
0.20
0.00
1
3
5
7
9
Signal line spacing (scaled)
55
Impact of Tiling on Physical Design Methodology

• Tiling is a PD Design CHANGE to Enhance Planarity
• Reticle Level Design - Resolution (Better Depth
  of Focus)
• Timing of Critical Nets - Constraint for
  Optimization Problem
• Model Can Resolve Rule-based vs. Model-based
  Strategy
• Some Designs Become LESS Planar with Rule-based!
• Tiling may impact coupling and delay
• EM Modeling for Total Capacitance and Crosstalk
• Dependence on Grounding or Floating of Tiles
• Tile Size vs. Wire Pitch is Important
• Tiling May Cause Mask Verification Problems
• Solution Intelligent Mask Inspection - Dont
  Repair Tiles - Dont Use Tiles in Die-to-Die
  System

56
Todays Design-Manufacturing Interfaces
Library (Library Team)
Design Rules Device Models
Litho/Process (Tech. Development)
Layout libs (Corner Case Timing)
RET
Design (ASIC Chip)
Mask Dataprep (Mask House)
Layout (collection of
polygons ?)
Tapeout
Guardbanding all the way in all stages!! (e.g.
clock ACLV guardband 30)

• What do we lose ?
• Performance ? Too much worst-casing
• Turnaround time ? Huge OPC runtimes, overdesign
• Predictability ? RET is applied post-design
• Mask costs ? Overcorrection
• Designers intent ? RET is not driven by design

57
Symptoms Routing Rules (1)

• Minimum area rules and via stacking
• Stacking vias through multiple layers can cause
  minimum area violations (alignment tolerances,
  etc.)
• Via cells can be created that have more metal
  than minimum via overlap (used for intermediate
  layers in stacked vias)
• Multiple-cut vias
• Use multiple-cut vias cells to increase yield and
  reliability
• Can be required for wires of certain widths
• Multiple via cut patterns have different spacing
  rules
• Four cuts in quadrilateral five cuts in cross
  six cuts in 2x3 array
• With wide-wire spacing rules, complicates pin
  access
• Cut-to-cut spacing rules ? check both cut-to-cut
  and metal-to-metal when considering via-to-via
  spacing

58
Symptoms Routing Rules (2)

• Width- and Length-dependent spacing rules
• Width-dependent rules domino effects
• Variant parallel-run rule (longer parallel
  runs ? more spacing)
• Measuring length and width halo rules affect
  computation
• Influence rules or stub rules
• A fat wire, e.g., power/ground net, will
  influence the spacing rule within its
  surroundings ? any wire that is X um away from
  the fat wire needs to be at least Y um away from
  any other geometry.
• Example fat wire with thin tributaries
• bigger spacing around every wire within certain
  distance of the thin tributaries
• ECO insertion of a tributary causes complications
• Strange jogs and spreading when wires enter an
  influenced area

59
Example LEF/DEF 5.5, April 2003
60
Example LEF/DEF 5.5, April 2003
61
Symptoms Routing Rules (3)

• Density
• Grounded metal fills (dummy fill)
• Via isodensity rules and via farm rules (via
  layers must be filled and slotted, have
  width-dependent spacing rule analogs, etc.)
• Non-rectilinear (?-geometry) routing
• X-Architecture http//www.xinitiative.org/
• Y-Architecture http//vlsicad.ucsd.edu/Yarchitec
  ture/ , LSI Logic patents
• Landing pad shapes (isothetic rectangle vs..
  octagon vs.. circle), different spacings (1.1x)
  between diagonal and Manhattan wires, etc.
• More exceptions
• More non-default classes (timing, EM reliability,
  )
• Not just power and clock
• gt0.25um width may be wide ? many exceptions

62
Symptoms Routing Rules

• Degrade completion rates, runtime efficiency
• Postprocessing likely no longer suffices
• E.g., antennas
• There is no chip until the router is done
• Must / Should / Can tomorrows IC routers
  independently address these issues?

63
Lithography Bottleneck

• Lithography limitation is a key bottleneck in
  nanometer manufacturing
• Need extensive RET
• OPC
• PSM
• OAI
• However, RETs mostly are done post-layout
• Major impact from raising the abstraction level
  RET-aware layout optimization gt real DFM

64
Foundation of the DFM Solution

• Bidirectional design-manufacturing data pipe
• Fundamental drivers cost, value
• Pass functional intent to manufacturing flow
• Example RET for predictable timing slack,
  leakage, yield
• RETs should win , reduce performance variation
  
• ? cost-driven, parametric yield constrained RET
• Pass limits of manufacturing flow up to design
• Example avoid corrections that cannot be
  manufactured or verified ? e.g., design should be
  aware of metrology

65
Background Yield Loss by Via Failure
Xu et al, ASPDAc05

• Via failure is a major reason for yield loss
• Partial failure increases via resistance and
  deteriorates timing.
• Complete failure breaks the net.
• Redundant via a backup via adjacent to the
  single normal via.
• Redundant via insertion highly recommended by
  major foundries in 130nm process and below.
• Startups (Nannor)

66
Redundant Via Enhanced Routing

• Conventional routing. No redundant via for B.

• Redundant Via Enhanced Routing

67
Basic Concepts of Redundant Via Constraints

• On-track neighbor
• Off-track neighbor
• Degree of Freedom (DoF)
• Live via
• Dead via
• Critical via

68
Problem Formulation

• Maze routing with redundant via constraints
  (MRRVC)
• Find the shortest route for net m such that
• ,
  where DVi is the number
• of dead vias in net i, Ci is the constraint
  of net i.
• Delayed RV insertion to have a global picture
• Keep track of dead vias for routed nets and the
  new net to be routed
• A special case to demonstrate the concept
• Extended to the general case

69
Count Dead Vias

• Counting dead vias
• How many vias in the routed nets are killed by
  the new net?
• How many dead vias for the new net?

70
Counting Dead Vias in the New Net

• Assign one unit cost to the z-axis edge (new net)
  if it does not have free neighbor

71
Redundant Via Enhanced Routing Overview

• A maze routing algorithm with redundant via
  constraints.
• Feasibility of redundant via insertion is
  guaranteed by constraining the number of dead
  vias in each net.
• The routing problem is transformed to
  multi-constrained shortest path problem by
  assigning cost to each edge.
• A Lagrangian relaxation based algorithm is used.

72
Experimental Results
73
CMP-Aware Layout OptimizationXu et al, ASPDAC05

• Sub-wave length lithography
• Use of advanced RET technology OPC, PSM
• Quickly increasing data volume and mask
  complexity
• Soaring cost of photomask gt shuttle mask (also
  called multi-project wafer)

Sub-wave length gap (Source Synopsys)
74
Shuttle Mask Floorplanning

• Shuttle mask a good solution to share mask cost
• Multiple different chips on the same mask
• Mask cost shared based on the occupied area
• Ideal for prototype and low volume designs
• A floorplanning problem How to optimally place
  chips on the mask?

75
CMP Topography Variation

• CMP Topography variation
• T HMAX-HMIN..
• Observations
• Topography variation determines the depth of
  focus in lithography, an important factor of
  manufacturability.
• Topography variation is determined by the
  feature density distribution of the circuit
  layout.
• Feature density distribution varies with shuttle
  mask floorplans

76
CMP-aware Shuttle Mask Floorplanning

• Problem Description
• Given a set of chips to be placed on the
  shuttle mask, find a floorplan with the minimum
  cost function value. The cost function is a
  weighted combination of the area and the post-CMP
  topography variation of the floorplan.
• Questions to be answered
• How to evaluate the topography variation given a
  floorplan?
• How to minimize the topography variation given a
  floorplan?
• How to find the best floorplan?

77
2-D Low Pass Model

• The 2-D low pass model Ouma IITC98
• 
  
• where
• H is the matrix of height distribution of the
  layout after CMP.
• D is the matrix of feature density distribution
• C
• DFT and IDFT are discrete Fourier Transformation
  and its inverse.
• Question 1 is answered based on this model.

78
Dummy Feature Insertion

• By inserting dummy feature into the layout, we
  can change the matrix D to minimize the CMP
  topography variation HMAX-HMIN .
• Question 2 is formulated as
• Let
• 
  .
• Ask for
  subject to
• Question 2 can be solved optimally by linear
  programming Tian et al TCAD01.

79
Strategies of The Floorplanner

• A floorplanner can be designed to solve Question
  3 based on the following strategies.
• Using simulated annealing search to find a
  near-optimal solution, which has been widely used
  in floorplanning problems.
• Using a predictive function to estimate the
  topography variation of each floorplan. It takes
  time to evaluate the optimal solution to
  topography variation with dummy feature
  insertion. So it is not practical to perform
  during SA procedure.

80
The Framework of The Floorplanner

• begin
• x InitialSolution
• SA search with a predictive function f(x)
• SlidingAndRotation(x)
• DummyInsertion(x)
• output the best solution x
• end.

81
Predictive Functions 1

• We evaluate the topography variation without
  dummy feature using the 2-d low pass model.
• We assume the smaller the topography variation
  without dummy feature, the smaller the optimal
  variation with dummy feature.

82
Predictive Functions 2

• We expect a cell with large variation to have
  large capacity to insert dummy feature, which
  means more flexibility to adjust its feature
  density.
• We expect the total weighted variation to be
  small, which suggests the current floorplan is
  more flat.

83
Predictive Functions 3

• We want to count in white space and the cell with
  minimum height.
• We want to normalize the variation among
  different floorplan for a fair comparison.

84
Experimental Results
85
A Shuttle Mask Floorplan by AreaNSDH
86
OPC/RET-Aware Routing Huang, DAC04 Mitra et
al, DAC05
OPC friendly
Not OPC friendly
87
Notes on Regular Layout

• 65 nm has high likelihood for layouts to look
  like regular gratings
• Uniform pitch and width on metal as well as poly
  layers
• ? Predictable layouts even in presence of focus
  and dose variations
• More manufacturable cell libraries with regular
  structures
• New layout challenges (e.g., preserving
  regularity in placement)

88
Regular Layouts

• Standard cells
• high performance, high density, low part cost,
  low power
• escalating NRE, TAT, variability
• Programmable devices (FPGA)
• regular, predictable, fast TAT, low NRE
• low performance, low density, high part cost,
  high power
• Middle ground e.g. via programmability (eASIC,
  CMU)
• VPGA retain regularity, but remove field
  programmability
• Use only a few via masks to configure a circuit

Courtesy Center for Silicon System
Implementation, CMU.
89
Via Patterning
Connection made
Connection not made
Sample synthesis Results
Courtesy Center for Silicon System
Implementation, CMU.
90
Stochastic/Robust Optimizations

• Physical design is no longer deterministic
• An example probabilistic LP
• Problem Too slow and not at all scalable

91
Example Robustness Metric for Power Distribution

• Power distribution analysis by solving GVI
• G Conductance matrix of the power distribution
  network
• I Current requirements for sinks
• V IR drop (if Vdd is put to 0)
• V Peak IR drop (l-1 norm)
• Random variations
• G E.g., width and thickness variation
• I E.g., inaccurate estimation of peak currents

92
Example Robustness Metric for Power
Distribution (2)

• Perturbation analysis
• E random perturbation in G
• e random perturbation in I
• V IR drop map after perturbation
• GG-1 condition number measure of
  robustness

93
Mask Design Physical Design
Classic Design Flow
Design IP
Design IP
Design IP
Design IP
Design IP
Behavioral Synthesis Floorplan Physical Design
EDA TOOLS FLOW
Physical Design
Mask Shapes Are the Same as Design Shapes
Maskwriter
Lithography Process
Silicon Patterns
Future Fab White Paper 2004
W. Grobman
94
Mask Design Physical Design
RET-Incorporated into Design Flow
Design IP
Design IP
Design IP
Design IP
Design IP
Behavioral Synthesis Floorplan Physical Design
EDA TOOLS FLOW
Physical Design
Mask Shapes Not Equal To Design Shapes
RET TOOLS FLOW
Too Late Si-based Verification
RET Physical Design
Maskwriter
Lithography Process
Maskwriter Lithography Models
YIELD
Manufacturability Rule Checks (MRC)
Silicon Patterns
FUNCTION
Future Fab White Paper 2004
95
One-Pass Correct Design
One-Pass RET-Driven Design Flow
Design IP
Design IP
IP Block Physical Design
Design IP
Design IP
Design IP
RET TOOLS FLOW
CERTIFIED BLOCK AVAILABLE FOR ASSEMBLY INTODESIGN
EDA TOOLS FLOW
Maskwriter Lithography Models
Physical Design
Virtual Silicon Patterns
RET TOOLS FLOW
Feedback Manufacturing Models With Framework Such
As The Universal Data Model
REDESIGN
Manufacturability Rule Checks (MRC)
RET Physical Design
Maskwriter
YES!
Yield Function OK?
Lithography Process
Yield Function OK!
Silicon Patterns
NO
Future Fab White Paper 2004
96
One-Pass Correct Design
One-Pass RET-Driven Design Flow
Design IP
Design IP
IP Block Physical Design
Design IP
Design IP
Design IP
RET TOOLS FLOW
CERTIFIED BLOCK AVAILABLE FOR ASSEMBLY INTODESIGN
EDA TOOLS FLOW
Maskwriter Lithography Models
Physical Design
Virtual Silicon Patterns
Design Closure May Depend on Foundry Models For
SAME Design Foundry 1 - OK Foundry 2 - Not OK
RET TOOLS FLOW
Feedback Manufacturing Models With Framework Such
As The Universal Data Model
REDESIGN
Manufacturability Rule Checks (MRC)
RET Physical Design
Maskwriter
YES!
Yield Function OK?
Lithography Process
Yield Function OK!
Silicon Patterns
NO
Future Fab White Paper 2004
97
Conclusions

• Designer, physical design, and mask communities
  must work closer together to address the combined
  design and manufacturing closure
• Bidirectional design-mfg interaction
• Pass functional intent to mask and foundry flows
• Pass limits of mask and foundry flows up to
  design
• Examples
• Manufacturability and cost/value optimization
• Exploitation of systematic variations (e.g.,
  iso-dense)
• Composability
• Performance impact-limited dummy fill
• Intelligent mask data prep, restricted design
  rules, etc.
• Manufacturing-aware PD much work lies ahead