CE2810

1
Using the USART

• Configuration and Programming

2
Connection between two communicating serial
devices

• The Tx (transmit) line of one device is connected
  to the Rx (receive) line of the second device
• Both devices have to be configured identically
• Same baud rate, parity, data bits, stop bits

Tx
Tx
Rx
Rx
3
Configuration of the USART

• Various I/O registers are used to
• Control the configuration of the USART
• Baud rate (bits/s)
• Parity (even/odd/none)
• Number of data bits (4-9)
• Framing ( 1 or 2 stop bits)
• Represent the status of a recent transmission or
  reception
• Frame errors
• Data overrun errors
• Tx complete
• Rx complete

4
Lots of registers

• UCSRA USART Control/Status Register A
• Mainly status flags
• UCSRB USART Control/Status Register B
• Flags for enabling transmitting, receiving,
  interrupts
• UCSRC USART Control/Status Register C
• Mode selection
• UBRRH, UBRRL USART Baud Rate Registers
• Baud rate selection
• UDR USART Data Register
• Does two things at once
• Contains data to be transmitted, or
• Data that is received

5
Duality of UDR register

• UDR USART Data Register
• TXB and RXB I/O addresses overlap
• When UDR is read, the contents of the Receive
  Buffer (RXB) are first shifted into UDR, so that
  UDR contains the contents of RXB
• When UDR is written, the contents are shifted to
  the Transmit Buffer (TXB)

6
USART Baud Rate Registers

• URSEL Register select
• UCSRC I/O address overlaps with address of UBRRH.
• Set to 0 if writing this Register as UBRRH
  otherwise UCSRC
• UBRR110 Baud Rate select
• 12-bit register specifying the USART
  transmit/receive baud rate. Use the following
  table for calculating the value to place in these
  bits. BAUD is in bits/sec, fosc is the Atmega32
  clock frequency.

7
USART Control/Status Register B

• RXCIE Receive complete interrupt enable
• Set to enable Receive Complete Interrupt. Disable
  to avoid conflicts with Atmon.
• TXCIE Transmit complete interrupt enable
• Set to enable Transmit Complete Interrupt.
  Disable to avoid conflicts with Atmon.
• UDRIE Data Register Empty interrupt enable
• Set to enable UDRE Interrupt. Disable to avoid
  conflicts with Atmon.
• RXEN Receiver Enable
• Set to enable the USART Receiver
• TXEN Transmitter Enable
• Set to enable the USART Transmitter

8
USART Control/Status Register A contains status
bits you read

• RXC Receive complete
• Set when data is received in the Receive Buffer
  (RXB)
• TXC Transmit complete
• Set when data in the Transmit Buffer has been
  completely transmitted and no new data in UDR
  manually cleared by writing a 1 to this bit
• UDRE Data Register Empty
• Set when Transmit Buffer is ready to accept new
  data to be transmitted
• FE Frame Error
• Set when Data in Receive Buffer had a frame error
  detected
• DOR Data Overrun
• Set when Receive Buffer is full (but unread), and
  new data is coming in
• PE Parity Error
• Set when Data in Receive Buffer had a parity
  error detected (if parity checking was enabled)

9
USART Control/Status Registers B and C

• UCSZ2, UCSZ1, UCSZ0 Character size select
• Together, these set the number of data bits being
  transmitted or received
• Set these to (011) for 8 data bits see
  reference manual for other settings
• URSEL Register select
• UCSRC I/O address overlaps with address of UBRRH.
• Set to 1 when reading this Register as UCSRC
  otherwise UBRRH
• UMSEL Mode select
• Set to 0 for Asynchronous mode
• UPM1, UPM0 Parity mode select
• Parity disabled (00), Even (10), Odd (11),
  Reserved (01)
• USBS Stop bit select
• Set to 0 for framing using a single Stop Bit

10
How to use the USART

• Set baud rate via UBRRH and UBRRL
• Enable Transmit and Receive via UCSRB
• Disable all USART interrupts via UCSRB (to avoid
  Atmon conflicts)
• Set Parity, Data bits, Stop bits, Async via
  UCSRC
• To Receive
• Poll UDRE bit in UCSRA until set
• Received char in UDR
• Repeat
• To Transmit
• Place character to be written in UDR
• Poll TXC bit in USCRA until set
• Repeat

11
The USART can receive while it is transmitting

• But the TXB and RXB buffers can each hold only
  one character
• So you must keep polling RXC to avoid dropping
  received characters
• And you must poll UDRE before sending another
  character to ensure that TXC has been emptied