News of the CALICE ECAL

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News of the CALICE - ECAL
1 - Progress report on the ECAL prototype 2 -
New informations on the costing of the ECAL 3
- A proposal for a new design of the detector
slab 4 - Conclusion
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Progress report on the prototype
Mid-march A first sample of tungsten plates
arrives at LLR metrology The design of the
front-end chip is fixed. First batch for
test. End-march production of the final set
of masks for the silicon wafers
processing Begining-april Start the
production of a sample of 40 tungsten plates
corresponding to the first technological test
and first stack of prototype April-May
Processing of the first 25 silicon wafers (DC
coupled) May-September Processing and test
of about 100 silicon wafers Final submission
of the VFE chip for the prototype
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Some interesting distribution (updated recently)
Moore's Law for Silicon Microstrip Detectors
2000 m²
1000
CMS
Silicon Area (m²)
GLAST
100
ATLAS
10
NOMAD
DO
CDF
AMS01
1
LEP
CDF
0.1
DATA From H.F-W. Sadrozinski, UC-Santa Cruz
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New elements for the costing of the ECAL
WARNING cost (2010) lt 2 /cm² is for
microstrip Processing
(Guestimate from H.S.)
Moore's Law for Silicon Detectors
50
BUT for ECAL W-Si
4''
Wafer size
6''
Number of masks (x 0.5 ) Industrial Yield (x
2 ) use of 8'' wafers ?
cost/area (/cm²)
10
Used in the TDR
At least a factor 2 cheaper is expected
ß
lt 2 /cm²
2
Blank wafer price 6''
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DATA From H.F-W. Sadrozinski, UC-Santa Cruz
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Re-calculate the estimation of cost, using the
2 ÿ/cm²for the silicon
The cost of the ECAL is between 68 (20 layers)
to 99 (40layers) Mÿ With the HCAL (i.e.
version DHCAL) , the total cost of the
calorimeter range from 129 (20 layers) to 175
(40 layers) MCH (CMS equivalent is 145
MCH) 1 - For the complete set ECAL HCAL
Muon-CH ( MCH) 2 - The change of the
geomerty can further reduce the cost
(length of barrel, internal radius,...)
18/40 reduction
CMS
216
Calice -FLC
132/178
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Why ?
There is a very small available space for the
VFE board (0.2x1x2cm³) Number of bonding/cm
on the VFE board (about 160/cm) Some risk of
pick-up noise (EMC) (coherent noise with 32
Mchannels) Number of wires/lines per cm in
the flex (from diodes to VFE) Industrial
feasability of all the processes COST
What else ?
START from usual electronics industrial processes
1 - Use PCB with low density readout strip
2 - Keep industrial yield of the silicon
diodes as high as possible 3 - Keep the small
thickness of the total 4 - Keep the pad size
open (from 0.5 to 1.5 cm) (SD, LD, ...or Rext.
TPC)
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Point 1 Multiplexing in the alveolus VFE
chip inside PCB low densitity
cooling inside ?? My comments UP to 200cm
PCB low density is quasi-INDUSTRIAL !
(130 cm is already in the box)
Point 2 VFE and Si wafer have indepedant
fabrication process Industrial Yield
(VFE is not bump bonded'' on the wafer)
VFE chip on one side of PCB and
diodes on the other My comments - No
thermal dissipation through the silicon wafer !
-Put a Si
wafer on one side and VFE chip
on the other side is
INDUSTRIAL ! !
Point 3 Thin packaging , large area VFE chip
Small overall thickness My comments
Thickness of the VFE-chip packaging R1mm is
INDUSTRIAL !
Point 4 The pad size depends on the
power/channel and cooling system Adaptable pad
size My comments The pad size
can be as low as 0.5 cm !

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Calculation by J.Badier (LLR) With 5mW/c
(which not so easy...)
1 - A cooling is NEEDED (at the middle of a
module , DTX 400) 2 - It is not so demanding
for the thickness
Rectangular tube 1mm x 20 mm
bar/m
DK
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AC coupling elements if needed
Budget (mm) 0.3 Al(sup) 0.1
Glue 1.0 VFE
Thermal contact if needed
Aluminium
0.3 mm
Cooling tube
Cooling tube
VFE chip
1.1 mm
X 2-3 cm
Powerline command line signal out
1.0 mm
PCB
Pad
0.5 mm
Silicon wafer
Conductive glue for electrical contact
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Advantages
A priori, all processes are uncorrelated (Si
wafer , VFE chip , PCB,...) we could expect a
good Industrial Yield A priori, all processes
are (quasi-) industrial The mounting of the
detector slab is a classical job for electronics
industry Probably easier access to VFE board
(not so trivial argument) Technically, There
is interesting challenges, BUT there are no
orders of magnitude to gain
Problems
What is the VFE chip behavior when a 400 GeV
e.m. Shower goes through ??
Could (and will) be rapidly tested
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Here dessin
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Progress report on the prototype Tungsten,
first plates arrived, first sample soon in
production Silicon wafers, final masks have been
designed VFE chip is in production for the first
batch (test)
Costing of the CALO. For FLC The project is in
the extrapolation of the Moore's law for the
cost and area of silicon to be processed Very
probably, the processed silicon wafers will be
lt2/cm ² Even with W-Si Ecal , there is an
important reduction when compared to the
equivalent in CMS
New design of the detector slab A lot of
advantages - INDUSTRIAL processes The
extrapolation from VFE chip is reasonable The
extrapolation for the readout lines is reasonable