Interfacing the Universal Controller to the Virtual Test Bed via Processor in the Loop

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Interfacing the Universal Controller to the
Virtual Test Bed via Processor in the Loop
VTB Conference 2005 Sep. 21, 2005

• R. Liu, R. Burgos, F. Wang, D. Boroyevich, A.
  Monti
• University of South Carolina
• Virginia Tech

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Outline

• Introduction
• System Structure of the VTB-UC Processor In the
  Loop (PIL) Simulation
• VTB-UC Project Tasks
• Preliminary Results
• Future Work

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Introduction(Background)

• Processor In the Loop (PIL) Definition
• The PIL is a testing procedure for
  micro-controller based control where the real
  final target is adopted for software testing.
• The control software interacts with a simulated
  model of the plant (no real-time constraint)

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Introduction

• Main components in this project

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Introduction

• Universal Controller (UC)

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Introduction
Distributed Power Electronics Control Architecture
Information System
Decreasing application dependence of modules
Increasing Reaction Speed
Universal Controller
Control Network
PEBBs
Electric Power System
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System Structure of the VTB-UC Processor In the
Loop (PIL) Simulation
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System Structure of the VTB-UC Processor In the
Loop (PIL) Simulation
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VTB-UC Simulation Timing Diagram
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VTB-UC Project Tasks

• VT tasks
• Define I/O signals
• Verify PCI interface in UC
• FPGA control module for Cypress chip
• DSP code
• Adapt UC for VTB-simulation mode
• Not in real time
• USC tasks
• Model UC PIL interface component
• Program VTB to run in PIL mode with external UC

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VTB-UC Project Tasks

• 3. Define PCI-bus interface between UC VTB
• Determine information to be transferred based on
  possible applications
• Determine VTB-UC communication mode (e.g.
  interruption or querying etc)

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Preliminary Results

• Finish demo PIL Interface component
• - Input signals
• 14 double data
• 16 flags
• - Output signals
• 10 double data
• 16 flags

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Preliminary Results

• Mux and Demux models
• Reason to develop Mux and Demux models
• Reduce the input / output ports
• Use less memory
• Convenient for designer to check
• Realization
• For Mux model
• Input flags (input 0 to input 15)
  1,0,0,1,0,0,1,1,1,1,1,1,0,1,1,1) Output 61385
  (1110111111001001)
• For DeMux, vice versa

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Preliminary Results

• Triangle wave model
• This model is used for synchronizing UC and
  plant in every sampling period STs.

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Preliminary Results

• Definition of PIL interface I/O signals
• Verification of PCI interface in UC
• FPGA control module for Cypress chip
• DSP code
• Verification of PCI interface in VTB interfacing
  component

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Future Work

• Adapt UC for VTB-UC PIL interface component
• Develop a flexible PIL interface component