Concurrent Wire Spreading, Fattening and Filling

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Concurrent Wire Spreading, Fattening and Filling

• Olivier Rizzo
• Hanno Melzner
• April 13th , 2007

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Concurrent Wire Spreading, Fattening and Filling

• Yield loss related to random defects
• CA reduction objective
• Improved metal density uniformity
• Proposed solution and algorithm overview
• Solution application to full chip layout
• New challenges and counter actions
• Experimental results
• Yield gain
• Timing and power characterization
• Outlook and summary

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Yield Loss Related to Random Defects

• Yield loss caused by random defects
• Critical area is the area in the design where
  circuit failures are most likely to occur

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CA Reduction Objective

• Opens and shorts play a major role inCu
  damascene technology
• Wire spreading and widening must beevenly
  considered
• Jogs increase metal length and OPCdata volume
• Reduce jogs count and length
• Improve jogs robustness
• To use the available room evenly, wire fattening
  and spreading must be concurrent

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Improved Metal Density Uniformity

• Reduce density variation to target 50metal
  density
• Use of track fill pattern to increase logicmetal
  density

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Proposed Solution and Algorithm Overview

• Bricking step
• Conductor splitting into small rectangles for CA
  optimization
• Analysis of bricks neighbouring shapes to find
  available space and constraints for CA
  improvement

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Proposed Solution and Algorithm Overview

• Widen the brick according to available space and
  estimate loss function from distances to
  neighbors
• Calculate upper boundaries position as per design
  rules
• Find CA optimum which minimizes the loss function
• Align edges to neighbors using anti-jog bonus
  to avoid unnecessary jogs and find new CA optimum
• Move brick to optimum position
• Do this for all bricks
• Iterate a few times until it is stabilized

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Proposed Solution and Algorithm Overview

• Iterations to find optimum width spacing ratio

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Proposed Solution and Algorithm Overview

• Polygon simplification to merge continuous
  rectangles and reduce data volume
• Track fill insertion
• Fill in empty spaces with regular track structure
• Use specific width and spacing to avoid OPC

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Solution Application to Full Chip Layout
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New Challenges and Counter Actions

• Jog optimization
• Avoid unnecessary jogs
• Manufacture friendly jogging style
• Impact on RC and timing
• Impact on antenna design rule violations
• Wire widening increase metal gate, area ratio
• Track fill
• OPC free track fill pattern to reducedata volume

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New Challenges and Counter Actions

• Impact on timing performance
• Reduced wire resistance and coupling capacitance
• Increased wire grounded capacitance

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Experimental Results

• YB yield gain is 1.7
• Yield gain mainly derives from lower logicfails
  fall out

Fattening
Spreading
Filling
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Experimental Results

• Timing performance is 3-5 less on characterized
  data
• Power consumption at the same frequency is 1
  less

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Outlook and summary

• Spreading Fattening and Filling on Silicon
• Overall gain YB 1.7
• Yield gain thanks to lower logic fails fall out
• Timing characterization is on spec
• Further steps
• Improve CA in logic area, RAMs and ROMs
• Improve floating metal shape parasitic extraction
  accuracy
• Consider DFM and Reliability optimization