Introduction to 8086

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Introduction to 8086

• UNIT XI
• Book Microprocessor 8086
• -By Sunil Mathur
• Topics 2.1, 2.2, 4.1, 4.2.1, 4.3, 4.5

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The 8086 Microprocessor

• It consists of two main section
• Bus Interface Unit (BIU)
• Execution unit (EU)
• Two units are independent of each other
• EU contains the ALU, flags, and general purpose
  registers
• All registers are 16-bits wide
• The BIU controls the address, data and control
  buses

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Fig 2.1 on page 28
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BIU

• It consists of the following
• Queue
• Segment Register
• Instruction pointer and address summation

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Queue

• Queue
• FIFO registers arranged like pipe called queue
• The BIU continuously fetch operations from the
  memory while the processor is executing current
  instruction
• BIU units stores the fetched bytes in the queue
  and the EU will read these bytes from the queue

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Segment register

• Segment register
• 1 MB memory is divided into segment
• Microprocessor 8086 can at a time access four
  segments
• Each segment is independent and up to 64K bytes
  long
• 8086 consists of 4 segment registers

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• Code Segment Register
• Stores base address of 64 KB segment and
  microprocessor instructions / programs
• The instruction pointer is the by default
  registers used by the microprocessor to access
  the instructions from the CS

8

• Stack Segment Register
• Contains the off set address of 64 KB segment
• Used as stack memory, operates on LIFO
• Performs Stack operations (PUSH and POP)

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• Data Segment Register
• Holds the logical address of 64 KB long data
  segment
• By default registers of this segment are
• AX
• BX
• CX
• DX
• Indexed register (SI and DI)

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• Extra Segment Register
• Contains the starting address of 64 KB segment
• This segment is the destination for the string
  data pointed by DI register (location pointed by
  DI register is stored here)
• Can not initialize ES register but can be changed
  using POP instruction

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Instruction Pointer and Address Summation

• It contains the offset / logical address of the
  next byte to be read from the code segment
• Generation of 20 bite physical address Example
  figure page no 31

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Execution Unit

• Consist of four 16-bit general purpose register
  AX, BX, CX, DX Which is divided among two parts
  ( higher and lower parts 8 bits each)
• Table
• AX register used as 16 bit accumulator in 16-bit
  operations whereas AL is used for 8 bit
  operation
• BX used as memory pointer in DS. Used for based,
  based indexed or register indirect addressing mode

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• CX (count register)
• used as counter in string manipulation. Default
  counter in loop instruction
• Data register DX
• consists of 2 8-bit registers DL and DH, which
  can be combined together and used as a 16-bit
  register DX. When combined, DL register contains
  the low-order byte of the word, and DH contains
  the high-order byte

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• Pointer and Base register
• Stack pointer
• Always points to top item on the stack
• Offset address relative to SS
• Always points to word (byte at even address)
• An empty stack will had SP FFFEh
• Base pointer
• Primarily used to access parameters passed via
  the stack
• Offset address relative to SS

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• SI - source index register
• Can be used for pointer addressing of data
• Used as source in some string processing
  instructions
• Offset address relative to DS
• DI - destination index register
• Can be used for pointer addressing of data
• Used as destination in some string processing
  instructions
• Offset address relative to ES

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Flag Register

• 8086 consists of one 16 bit flag register (set of
  16 independent flip flops)
• 6 flip flops are used to indicate data conditions
  
• 3 F.F used to control some machine control
  operations
• 7 FF are reserved for upcoming microprocessor

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Flag Register
X X X X OF DF IF TF SF ZF X AF X PF X CF
Overflow
Trap
parity
Auxiliary carry
Zero
Direction
Carry
Sign
Interrupt Enable
Six Status flags, 3 Control Flags Bits marked X
undefined
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Status Flags

• Zero flag (ZF)
• Indicates weather the result of mathematical/
  logical operation is zero / non zero.
• result 0 (bit set)
• Result 0 (bit clear)
• Carry Flag (CF)
• When carry / borrow is generated out of most
  significant bit position, this flag is set.

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• Sign Flag (SF)
• Indicates the result of mathematical operation is
  positive or negative.
• Positive result bit is clear (0)
• Negative result bit is set (1)
• Parity Flag (PF)
• Indicates whether the number set bits (1 s) is
  odd or even in the binary result.
• Result Odd Parity (Bit is Clear)
• Result Even Parity (Bit is Set)

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• Auxiliary Carry Flag (AC)
• Used to show the carry propagation from one
  position to another.
• Used to convert binary result to BCD.
• Ex.
• 1 0 0 0 1 1 0 0
• 0 0 1 0 1 0 1 1
• Overflow Flag (OF)
• Used in signed arithmetic operations.
• Ex.
• 1 1 0 0 1 1 0 0
• 1 1 1 0 1 0 1 1

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Control Flags(used to control the operations of
processors)

• Trap Flag (TF)
• If set, single step interrupt occur after the
  execution of the next instruction.
• Used for single step debugging
• Interrupt Enable Flag (IF)
• when this flag is set to 1 CPU reacts to
  interrupts from external devices
• Direction Flag (DF)
• Used in string related operation.
• when this flag is set to 0 - the processing is
  done forward,
• when this flag is set to 1 the processing is done
  backward.

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Instructions Set of 8086

• Instructions are the directions which a
  microprocessor follows to execute a task or part
  of a task
• Low level Language High Level Language
• Low Level Language is divided into Machine
  Language and Assembly Language
• Instructions written in English like language
  (using alphabets) is known as Assembly Language.
• Instructions in this language are termed as
  Mnemonics.

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Addressing Modes of 8086

• Way of specifying an operand in an instruction.
• Categorized into 2 groups
• Data addressing modes (in 8085)
• Implied
• Register
• Immediate
• Direct
• Register Indirect
• Along with this 8086 also have
• Base addressing mode
• Indexed addressing mode
• Based indexed addressing mode
• Based indexed with displacement addressing mode
• String addressing mode
• Address addressing modes

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Immediate Addressing Mode

• Operands are specified within the instruction
  itself.
• Ex MOV AX, 2500H

Register Addressing Mode

• The content of a register can be accessed by
  specifying the name of the register as an operand
  to the instruction
• Ex. MOV AX, BX

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Direct / Displacement only Addressing Mode

• Address of the memory is specified in the
  instruction itself
• Ex MOV BL, 2005H MOV 2000H, DL
• MOV AX, ES 4321H MOV AX, CS 4321H
• bracket indicates memory location

Register Indirect Addressing Mode

• Memory address is specified by some pointer,
  index or base register
• Ex. MOV DX, BX MOV DX, BP
• MOV DX, SI MOV DX, DI
• BX, SI, DI Mode use DS by default
• BP Mode use SS by default
• To access data from other than default segment,
  segment override prefix symbol are to be used.
• MOV AX, DSBP

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Base Addressing Mode

• 8 bit / 16 bit displacement is added to the
  contents of a base register (BX / BP).
• Resulting value is a pointer to location where
  data resides.
• Ex MOV AL, BX 15
• The displacement can also be written as
• MOV AL, DISP BX
• BX Default Data Segment
• BP Default Stack Segment
• Segment override prefixes can be used to specify
  different segments
• MOV AL, SS DISP BX
• MOV AL, ES DISP BP

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Index Addressing Mode

• 8 bit / 16 bit displacement is added to the
  contents of a index register (SI / DI).
• Resulting value is a pointer to location where
  data resides.
• Ex MOV AL, SI 15
• SI / DI Default Data Segment
• Segment override prefixes can be used to specify
  different segments
• MOV AL, CS DISP SI
• MOV AL, SS DISP DI

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Based indexed addressing mode

• The content of the base registers BP / BX are
  added to the content of the index register SI /
  DI.
• Resulting value is a pointer to location where
  data resides.
• EX MOV AL, BXSI
• MOV AL, BPDI
• If BX 2000H and SI 5400H, the instruction is
• MOV AL, BX SI
• Therefore The content of the memory location
  
• 7400H is transferred to AL
  register.

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Based indexed with displacement addressing mode

• 8 bit / 16 bit displacement is added to the
  content of a base register (BX / BP) and index
  register (SI / DI).
• The resulting value is a pointer to the location
  where data resides.
• Ex. If BX 2000H , SI 5400H the instruction
  MOV AL, BX SI 15
• The content of the memory location 740FH is
  transferred to AL register.

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String Addressing Mode

• The string instruction automatically assumes SI
  to point to the first byte or word of the source
  operand and DI to point to the first byte or word
  of the destination operand.
• The segment register for the source is DS, and
  overridden.
• The segment register for the destination is ES,
  and cant be overridden.
• Content of SI and DI can be incremented by
• (Direction Flag) DF 0 (CLD instruction)
• Content of SI and DI can be decremented by
• (Direction Flag) DF 1 (STD instruction)

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Instruction Format

• 1 to 6 byte long
• Different Formats of Instructions

OP CODE
OP CODE REG
OP CODE MOD REG R / M
OP CODE MOD REG R / M Lower Disp Higher Disp
OP CODE MOD REG R / M Lower Disp Higher Disp Lower Data Higher Data
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• Opcode may be of 8 bits / may occupy MSB 6 bits
  of the 1st byte. And defines operation to be
  carried out
• Remaining 2 bits are any of the following bits.

Field Value Function
S 0 1 No Sign Extension Sign Extended 8 bit (if w1)
W 0 1 Instruction operates on byte data Instruction operates on word data
D 0 1 Instruction source is specified in Reg field. Inst. destination is specified in Reg field.
V 0 1 Shift / Rotate count is 1 Shift / Rotate count is specified in CL reg.
Z 0 1 Repeat / Loop while zero flag is clear Repeat / Loop while zero flag is set
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MOV instruction ( Data Transfer Instruction)

• Copies the second operand (Source) to the first
  operand (Destination)
• Both operands must be of same size (byte / word)
• Registers can be any of the general purpose reg.
• Operands can be of types
• MOV REG, memory
• MOV memory, REG
• MOV REG, REG
• MOV memory, immediate
• MOV REG, immediate
• MOV SREG, memory
• MOV memory, SREG
• MOV REG, SREG,
• MOV SREG, REG

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MOV instruction ( Data Transfer Instruction)

• Memory can be specified by any of the memory
  related addressing modes
• Immediate data can only be specified at the
  source
• Invalid move instructions are
• Segment to segment
• Memory to memory
• Memory to IO
• IO to memory
• IO to IO ( IO can communicate only with
  accumulator )
• Immediate data cannot be transferred to segment
  register.
• Move to and from segment reg. are always 16 bits.
• MOV inst. cannot set the value of CS and IP
  register.
• In MOV inst. the flag remains unchanged.

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Example

• If we want to initialize the DS by a memory
  location 2500H then first we have to load the
  value 2500H into AX register and then
  transferring contents of AX to DS
• MOV AX, 2500H
• MOV DS, AX

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Arithmetic Instructions

• ADD
• Operands REG, memory
• memory, REG
• REG , REG
• REG, immediate
• Memory, immediate
• Ex. Add instruction used to perform the operation
  F X Y Z
• MOV AX, X
• ADD AX, Y
• Add AX, Z
• MOV F, AX
• Flag bits are modified as per the result of the
  operation.
• Segment register can not be used as an operand in
  the ADD instruction.

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• SUB
• Operands REG, memory
• memory, REG
• REG, REG
• memory, immediate
• REG, immediate
• Ex. MOV AL, 05H
• SUB AL, 02H
• result in AL 03H

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• INC (Increment)
• Operands REG
• Memory
• This instruction differs with the ADD by 1
  instruction.
• INC does not affect CF (carry Flag) whereas the
  ADD inst. Modifies CF.
• INC is more compact instruction (only 1 byte).
• Faster than the comparable ADD instruction.
• DEC (Increment) (Same as above)

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• DIV (Unsigned division)
• Operand REG
• memory
• Divides the content of the AX or the DXAX by a
  specified source operand.
• Both operands are unsigned.
• If divisor is 16 bits then the dividend is the
  DXAX register pair.
• In the result the quotient is stored in AX and
  the remainder in DX.
• If divisor is 8 bits then the dividend is the AX
  register.
• In the result the quotient is stored in AL and
  the remainder in AH.
• Ex. MOV AX, 00C8H MOV CL, 06H DIV
  CL

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• MUL (Multiplication)
• Operands REG
• Memory
• Multiplies the content of AL / AX by a specified
  source operand.
• For 16 bit multiplication the implied operand
  will be AX register. After multiplication, 32 bit
  product will be stored in DXAX reg. pair.
• For 8 bit multiplication the implied operand will
  be AL register. After multiplication, 16 bit
  product will be stored in AX reg.
• If the result in DX / AH is not zero, the carry
  Flag (CF)and overflow flags (OF) will be set.
• Ex. MOV AL, 0FDH MOV CL, 05H MUL CL
• Result in AX 04F1H

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• NEG (Negate)
• Operands REG
• Memory
• Produces the 2s compliment of specified operand.
• Stores the result in the same operand.
• All the flags will be affected as per the result.
• Non-Zero Operand --- Carry Flag 1
• Zero Operand --- Carry Flag 0
• Ex. MOV AL, 15H
• NEG AL
• Result in AL 0EBH (2s complement of 15H)

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Logical Instructions

• AND
• Operands REG, memory
• memory, REG
• REG, REG
• memory, immediate
• REG, immediate
• Performs bitwise Logical AND of destination
  operand and the source operand. The result of the
  operation is stored in the destination operation.
• Z, P, and S flag bits are modified as per the
  result
• Carry and Overflow flags are 0. (Auxiliary Flag)
  AC 0 / 1
• Ex. MOV AL, 61H AL 01100001
• AND AL, CFH AL 01000001

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• CMP (Compare)
• Operands REG, memory
• memory, REG
• REG, REG
• memory, immediate
• REG, immediate
• Compares the source operand with the destination
  operand.
• Microprocessor subtracts source operand from the
  destination operand, but none of the operands are
  modified.
• Used for conditional control transfer
  instructions.
• Result is reflected by flag bits.
• Unsigned comparison Carry and Zero flag.
• Signed Comparison Zero, Sign, Overflow.

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• Unsigned Comparison Operation
• If AX BX, Result 0 , ZF 1
• If AX gt BX, Result 0 and Ve, ZF 0, CF 0
• If BX gt AZ, Result is Ve, ZF 0, CF 1
• Signed Comparison Operation
• Perform XOR operation of Sign and Overflow flag.
  ( in XOR No. of 1s is even then
  result 0, else 1 )

Sign Flag Overflow Flag Result
0 1 AX lt BX (-Ve)
1 0 AX lt BX (-Ve)
0 0 AX gt BX (Ve)
1 1 AX gt BX (Ve)
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• NOT (Logically Not)
• Operands REG
• Memory
• Complements individual bits of operand and save
  the result in same operand.
• Flag register remain unmodified.
• Ex. MOV AL, 39H
• NOT AL
• Result AL C6H

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• OR (Logically OR)
• Operands REG, memory
• memory, REG
• REG, REG
• memory, immediate
• REG, immediate
• Performs bitwise logical OR operation between
  source and destination operand.
• Result is stored in destination operand.
• Z, S, P flags are modified
• CF and OF (flags) 0
• AC Flag undefined.
• XOR works exactly similar to OR operation except
  the rule of XOR.