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CMOS VLSI

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CMOS VLSI Digital Design Overview Physical principles Combinational logic Sequential logic Datapath Memories Trends Dopants Silicon is a semiconductor Pure silicon ... – PowerPoint PPT presentation

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Title: CMOS VLSI


1
CMOS VLSI
  • Digital Design

2
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

3
Dopants
  • Silicon is a semiconductor
  • Pure silicon has no free carriers and conducts
    poorly
  • Adding dopants increases the conductivity
  • Group V extra electron (n-type)
  • Group III missing electron, called hole (p-type)

4
nMOS Operation
  • Body is commonly tied to ground (0 V)
  • When the gate is at a low voltage
  • P-type body is at low voltage
  • Source-body and drain-body diodes are OFF
  • No current flows, transistor is OFF

5
Transistors as Switches
  • We can view MOS transistors as electrically
    controlled switches
  • Voltage at gate controls path from source to drain

6
CMOS Inverter
A Y
0
1
7
Inverter Cross-section
  • Typically use p-type substrate for nMOS
    transistors
  • Requires n-well for body of pMOS transistors

8
Inverter Mask Set
  • Transistors and wires are defined by masks
  • Cross-section taken along dashed line

9
Fabrication Steps
  • Start with blank wafer
  • Build inverter from the bottom up
  • First step will be to form the n-well
  • Cover wafer with protective layer of SiO2 (oxide)
  • Remove layer where n-well should be built
  • Implant or diffuse n dopants into exposed wafer
  • Strip off SiO2

10
Oxidation
  • Grow SiO2 on top of Si wafer
  • 900 1200 C with H2O or O2 in oxidation furnace

11
Photoresist
  • Spin on photoresist
  • Photoresist is a light-sensitive organic polymer
  • Softens where exposed to light

12
Lithography
  • Expose photoresist through n-well mask
  • Strip off exposed photoresist

13
Etch
  • Etch oxide with hydrofluoric acid (HF)
  • Seeps through skin and eats bone nasty stuff!!!
  • Only attacks oxide where resist has been exposed

14
Strip Photoresist
  • Strip off remaining photoresist
  • Use mixture of acids called piranah etch
  • Necessary so resist doesnt melt in next step

15
n-well
  • n-well is formed with diffusion or ion
    implantation
  • Diffusion
  • Place wafer in furnace with arsenic gas
  • Heat until As atoms diffuse into exposed Si
  • Ion Implanatation
  • Blast wafer with beam of As ions
  • Ions blocked by SiO2, only enter exposed Si

16
Simplified Design Rules
  • Conservative rules to get you started

17
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

18
Complementary CMOS
  • Complementary CMOS logic gates
  • nMOS pull-down network
  • pMOS pull-up network
  • a.k.a. static CMOS

Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
19
Gate Layout
  • Layout can be very time consuming
  • Design gates to fit together nicely
  • Build a library of standard cells
  • Standard cell design methodology
  • VDD and GND should abut (standard height)
  • Adjacent gates should satisfy design rules
  • nMOS at bottom and pMOS at top
  • All gates include well and substrate contacts

20
Example NAND3
  • Horizontal N-diffusion and p-diffusion strips
  • Vertical polysilicon gates
  • Metal1 VDD rail at top
  • Metal1 GND rail at bottom
  • 32 l by 40 l

21
I-V Characteristics
  • In Linear region, Ids depends on
  • How much charge is in the channel?
  • How fast is the charge moving?

22
Channel Charge
  • MOS structure looks like parallel plate capacitor
    while operating in inversion
  • Gate oxide channel
  • Qchannel CV
  • C Cg eoxWL/tox CoxWL
  • V Vgc Vt (Vgs Vds/2) Vt

Cox eox / tox
23
Carrier velocity
  • Charge is carried by e-
  • Carrier velocity v proportional to lateral
    E-field between source and drain
  • v mE m called mobility
  • E Vds/L
  • Time for carrier to cross channel
  • t L / v

24
nMOS Linear I-V
  • Now we know
  • How much charge Qchannel is in the channel
  • How much time t each carrier takes to cross

25
Example
  • Example a 0.6 mm process from AMI semiconductor
  • tox 100 Å
  • m 350 cm2/Vs
  • Vt 0.7 V
  • Plot Ids vs. Vds
  • Vgs 0, 1, 2, 3, 4, 5
  • Use W/L 4/2 l

26
Capacitance
  • Any two conductors separated by an insulator have
    capacitance
  • Gate to channel capacitor is very important
  • Creates channel charge necessary for operation
  • Source and drain have capacitance to body
  • Across reverse-biased diodes
  • Called diffusion capacitance because it is
    associated with source/drain diffusion

27
Gate Capacitance
  • Approximate channel as connected to source
  • Cgs eoxWL/tox CoxWL CpermicronW
  • Cpermicron is typically about 2 fF/mm

28
Diffusion Capacitance
  • Csb, Cdb
  • Undesirable, called parasitic capacitance
  • Capacitance depends on area and perimeter
  • Use small diffusion nodes
  • Comparable to Cg
  • for contacted diff
  • ½ Cg for uncontacted
  • Varies with process

29
RC Delay Model
  • Use equivalent circuits for MOS transistors
  • Ideal switch capacitance and ON resistance
  • Unit nMOS has resistance R, capacitance C
  • Unit pMOS has resistance 2R, capacitance C
  • Capacitance proportional to width
  • Resistance inversely proportional to width

30
Interconnect
  • Chips are mostly made of wires called
    interconnect
  • In stick diagram, wires set size
  • Transistors are little things under the wires
  • Many layers of wires
  • Wires are as important as transistors
  • Speed
  • Power
  • Noise
  • Alternating layers run orthogonally

31
Wire Capacitance
  • Wire has capacitance per unit length
  • To neighbors
  • To layers above and below
  • Ctotal Ctop Cbot 2Cadj

32
Lumped Element Models
  • Wires are a distributed system
  • Approximate with lumped element models
  • 3-segment p-model is accurate to 3 in simulation
  • L-model needs 100 segments for same accuracy!
  • Use single segment p-model for Elmore delay

33
Crosstalk
  • A capacitor does not like to change its voltage
    instantaneously.
  • A wire has high capacitance to its neighbor.
  • When the neighbor switches from 1-gt 0 or 0-gt1,
    the wire tends to switch too.
  • Called capacitive coupling or crosstalk.
  • Crosstalk effects
  • Noise on nonswitching wires
  • Increased delay on switching wires

34
Coupling Waveforms
  • Simulated coupling for Cadj Cvictim

35
Noise Implications
  • So what if we have noise?
  • If the noise is less than the noise margin,
    nothing happens
  • Static CMOS logic will eventually settle to
    correct output even if disturbed by large noise
    spikes
  • But glitches cause extra delay
  • Also cause extra power from false transitions
  • Dynamic logic never recovers from glitches
  • Memories and other sensitive circuits also can
    produce the wrong answer

36
Advanced Circuits
  • What makes a circuit fast?
  • I C dV/dt -gt tpd ? (C/I) DV
  • low capacitance
  • high current
  • small swing
  • Logical effort is proportional to C/I
  • pMOS are the enemy!
  • High capacitance for a given current
  • Can we take the pMOS capacitance off the input?
  • Various circuit families try to do this

37
Pseudo-nMOS
  • In the old days, nMOS processes had no pMOS
  • Instead, use pull-up transistor that is always ON
  • In CMOS, use a pMOS that is always ON
  • Ratio issue
  • Make pMOS about ¼ effective strength of pulldown
    network

38
Dynamic Logic
  • Dynamic gates uses a clocked pMOS pullup
  • Two modes precharge and evaluate

39
The Foot
  • What if pulldown network is ON during precharge?
  • Use series evaluation transistor to prevent fight.

40
Monotonicity
  • Dynamic gates require monotonically rising inputs
    during evaluation
  • 0 -gt 0
  • 0 -gt 1
  • 1 -gt 1
  • But not 1 -gt 0

41
Domino Gates
  • Follow dynamic stage with inverting static gate
  • Dynamic / static pair is called domino gate
  • Produces monotonic outputs

42
Pass Transistor Circuits
  • Use pass transistors like switches to do logic
  • Inputs drive diffusion terminals as well as gates
  • CMOS Transmission Gates
  • 2-input multiplexer
  • Gates should be restoring

43
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

44
Sequencing
  • Combinational logic
  • output depends on current inputs
  • Sequential logic
  • output depends on current and previous inputs
  • Requires separating previous, current, future
  • Called state or tokens
  • Ex FSM, pipeline

45
Sequencing Overhead
  • Use flip-flops to delay fast tokens so they move
    through exactly one stage each cycle.
  • Inevitably adds some delay to the slow tokens
  • Makes circuit slower than just the logic delay
  • Called sequencing overhead
  • Some people call this clocking overhead
  • But it applies to asynchronous circuits too
  • Inevitable side effect of maintaining sequence

46
Sequencing Elements
  • Latch Level sensitive
  • a.k.a. transparent latch, D latch
  • Flip-flop edge triggered
  • A.k.a. master-slave flip-flop, D flip-flop, D
    register
  • Timing Diagrams
  • Transparent
  • Opaque
  • Edge-trigger

47
Latch Design
  • Buffered output
  • No backdriving
  • Widely used in standard cells
  • Very robust (most important)
  • Rather large
  • Rather slow (1.5 2 FO4 delays)
  • High clock loading

48
Sequencing Methods
  • Flip-flops
  • 2-Phase Latches
  • Pulsed Latches

49
Clocking Summarized
  • Flip-Flops
  • Very easy to use, supported by all tools
  • 2-Phase Transparent Latches
  • Lots of skew tolerance and time borrowing
  • Pulsed Latches
  • Fast, some skew tol borrow, hold time risk

50
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

51
Full Adder
  • Brute force implementation from eqns

52
Carry-Skip Adder
  • Carry-ripple is slow through all N stages
  • Carry-skip allows carry to skip over groups of n
    bits
  • Decision based on n-bit propagate signal

53
Tree Adder
  • If lookahead is good, lookahead across lookahead!
  • Recursive lookahead gives O(log N) delay
  • Many variations on tree adders
  • Brent-Kung 2N gates, 2lg N depth
  • Sklansky 0.5N lg N gates, lg N depth, high
    fanout
  • Kogge-Stone N lg N gates, log N depth, 0.5 N
    tracks

54
Funnel Shifter
  • A funnel shifter can do all six types of shifts
  • Selects N-bit field Y from 2N-bit input
  • Shift by k bits (0 ? k lt N)

55
Funnel Shifter Design 1
  • N N-input multiplexers
  • Use 1-of-N hot select signals for shift amount
  • nMOS pass transistor design (Vt drops!)

56
Funnel Shifter Design 2
  • Log N stages of 2-input muxes
  • No select decoding needed

57
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

58
Memory Arrays
59
Array Architecture
  • 2n words of 2m bits each
  • If n gtgt m, fold by 2k into fewer rows of more
    columns
  • Good regularity easy to design
  • Very high density if good cells are used

60
6T SRAM Cell
  • Cell size accounts for most of array size
  • Reduce cell size at expense of complexity
  • 6T SRAM Cell
  • Used in most commercial chips
  • Data stored in cross-coupled inverters
  • Read
  • Precharge bit, bit_b
  • Raise wordline
  • Write
  • Drive data onto bit, bit_b
  • Raise wordline

61
SRAM Sizing
  • High bitlines must not overpower inverters during
    reads
  • But low bitlines must write new value into cell

62
Decoders
  • n2n decoder consists of 2n n-input AND gates
  • One needed for each row of memory
  • Build AND from NAND or NOR gates
  • Static CMOS Pseudo-nMOS

63
Decoder Layout
  • Decoders must be pitch-matched to SRAM cell
  • Requires very skinny gates

64
Sense Amplifiers
  • Bitlines have many cells attached
  • Ex 32-kbit SRAM has 256 rows x 128 cols
  • 128 cells on each bitline
  • tpd ? (C/I) DV
  • Even with shared diffusion contacts, 64C of
    diffusion capacitance (big C)
  • Discharged slowly through small transistors
    (small I)
  • Sense amplifiers are triggered on small voltage
    swing (reduce DV)

65
Queues
  • Queues allow data to be read and written at
    different rates.
  • Read and write each use their own clock, data
  • Queue indicates whether it is full or empty
  • Build with SRAM and read/write counters
    (pointers)

66
CAMs
  • Extension of ordinary memory (e.g. SRAM)
  • Read and write memory as usual
  • Also match to see which words contain a key

67
10T CAM Cell
  • Add four match transistors to 6T SRAM
  • 56 x 43 l unit cell

68
CAM Cell Operation
  • Read and write like ordinary SRAM
  • For matching
  • Leave wordline low
  • Precharge matchlines
  • Place key on bitlines
  • Matchlines evaluate
  • Miss line
  • Pseudo-nMOS NOR of match lines
  • Goes high if no words match

69
ROM Example
  • 4-word x 6-bit ROM
  • Represented with dot diagram
  • Dots indicate 1s in ROM

Word 0 010101 Word 1 011001 Word 2 100101 Word
3 101010
Looks like 6 4-input pseudo-nMOS NORs
70
ROM Array Layout
  • Unit cell is 12 x 8 l (about 1/10 size of SRAM)

71
Row Decoders
  • ROM row decoders must pitch-match with ROM
  • Only a single track per word!

72
PLAs
  • A Programmable Logic Array performs any function
    in sum-of-products form.
  • Literals inputs complements
  • Products / Minterms AND of literals
  • Outputs OR of Minterms
  • Example Full Adder

73
PLA Schematic Layout
74
PLAs vs. ROMs
  • The OR plane of the PLA is like the ROM array
  • The AND plane of the PLA is like the ROM decoder
  • PLAs are more flexible than ROMs
  • No need to have 2n rows for n inputs
  • Only generate the minterms that are needed
  • Take advantage of logic simplification

75
Overview
  • Physical principles
  • Combinational logic
  • Sequential logic
  • Datapath
  • Memories
  • Trends

76
Ideal nMOS I-V Plot
  • 180 nm TSMC process
  • Ideal Models
  • b 155(W/L) mA/V2
  • Vt 0.4 V
  • VDD 1.8 V

77
Simulated nMOS I-V Plot
  • 180 nm TSMC process
  • BSIM 3v3 SPICE models
  • What differs?
  • Less ON current
  • No square law
  • Current increases
  • in saturation

78
Velocity Saturation
  • We assumed carrier velocity is proportional to
    E-field
  • v mElat mVds/L
  • At high fields, this ceases to be true
  • Carriers scatter off atoms
  • Velocity reaches vsat
  • Electrons 6-10 x 106 cm/s
  • Holes 4-8 x 106 cm/s
  • Better model

79
Channel Length Modulation
  • Reverse-biased p-n junctions form a depletion
    region
  • Region between n and p with no carriers
  • Width of depletion Ld region grows with reverse
    bias
  • Leff L Ld
  • Shorter Leff gives more current
  • Ids increases with Vds
  • Even in saturation

80
Body Effect
  • Vt gate voltage necessary to invert channel
  • Increases if source voltage increases because
    source is connected to the channel
  • Increase in Vt with Vs is called the body effect

81
OFF Transistor Behavior
  • What about current in cutoff?
  • Simulated results
  • What differs?
  • Current doesnt go
  • to 0 in cutoff

82
Leakage Sources
  • Subthreshold conduction
  • Transistors cant abruptly turn ON or OFF
  • Junction leakage
  • Reverse-biased PN junction diode current
  • Gate leakage
  • Tunneling through ultrathin gate dielectric
  • Subthreshold leakage biggest source today

83
DIBL
  • Drain-Induced Barrier Lowering
  • Drain voltage also affect Vt
  • High drain voltage causes subthreshold leakage to
    ________.

84
Junction Leakage
  • Reverse-biased p-n junctions have some leakage
  • Is depends on doping levels
  • And area and perimeter of diffusion regions
  • Typically lt 1 fA/mm2

85
Gate Leakage
  • Carriers may tunnel thorough very thin gate
    oxides
  • Predicted tunneling current (from Song01)
  • Negligible for older processes
  • May soon be critically important
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