Senior Capstone Project GPS Signal Simulator

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Senior Capstone ProjectGPS Signal Simulator

• May 2, 2006
• Benjamin Herreid
• Anthony Hoehne
• Advisor Dr. In Soo Ahn
• Sponsored By

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Outline

• Project Description
• Block Diagram
• Software
• System Inputs
• GUI Application
• Software/Hardware Interface
• Hardware
• FPGA
• RF side
• Results and Future Work

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Project Summary

• Global Positioning System (GPS)
• Satellite based navigation system
• Guaranteed worldwide coverage
• Solve problem backwards
• Generate the simulated GPS signals for up to 4
  visible satellites (channels)
• Use generated signals to drive a commercial
  receiver

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Project Application

• Model a scenario that uses GPS signals
• Useful in developing a GPS receiver
• Much cheaper than physical testing
• Airplanes
• Spacecraft
• Tests that are impossible in real life
• Repeatability
• High-dynamics

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Equipment

• PC Windows XP, Parallel Port
• FPGA Altera Cyclone
• Altera UP3 Development Board
• D/A Converter, OpAmp
• MAX5184, 10 bits
• LM311
• Mixer and Oscillator
• RF Signal Generator
• Commercial Receiver
• Ashtech G8

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Block Diagram

• Input data GUI, Files
• Data from PC to FPGA
• 2kHz, Digital
• GPS Signal to Mixer
• Analog, IF 2.046 MHz
• Sampling Rate 8.184 MHz
• GPS Signal to Receiver
• Analog, L1 1.57542 GHz

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PC Data Path
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Trajectory File

• Proprietary
• Duration of Jerk
• 4 axes Roll, Pitch (Elevation), Yaw (Heading),
  Thrust

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Initial Conditions

• 3rd Derivative
• Requires initial conditions for lower order
  parameters
• Acceleration 0
• Velocity 0
• Attitude 0 (level, due North)
• Position Specified by User

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Almanac and Antenna Files

• Almanac File
• Standard - Rinex 2
• Ephemeris Data
• Antenna File
• Proprietary
• Antenna Gain
• Azimuth, Elevation

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Phase and Visibility Files

• Phase File
• Phase (distance) to each satellite in radians
• At fixed frequency, wavelength is constant so
  phase and distance are interchangeable (f?c)
• Visibility File
• Azimuth and Elevation of each satellite
• Signal Power from each satellite

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Application Screenshot
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Application Screenshot
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PC to FPGA Communication
4 Channels
Minimum Communication Rate 4 bytes/channel x 4
channels x 2kHz Update Rate 32kHz
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Outline

• Project Description
• Block Diagram
• Software
• System Inputs
• GUI Application
• Software/Hardware Interface
• Hardware
• FPGA
• RF side
• Results and Future Work

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FPGA Calculations
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Interpolation Wrapping
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Signal Spectrum
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RF Subsystem

• D/A converter
• MAX5184 10 bit
• 40MHz, Differential voltage output
• LM311 OpAmp
• Conversion to single-ended signal
• Mixer and signal generator
• Attenuation
• -130dBm required for receiver
• 90dB attenuation needed (-40dBm at D/A)

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Results

• PC
• GUI finished
• Individual programs run
• Data ready for packing
• FPGA
• Single channel nearly completed
• Problems with Quartus II
• RF
• D/A Not completed
• Mixer Experimented, not implemented

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Simulations
Interpolation and lookup table indexing
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Simulations
C/A code generation for SV 1 / Ch 1
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Future Work

• Establish Communication
• Add navigation data
• Additional features
• Ionosphere and troposphere effects
• Multipath
• Additional channels (multiple FPGAs)
• Instrument panel in GUI

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Questions?
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RF Experimenting