ESD for the Fabless Semiconductor Company

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ESD for the Fabless Semiconductor Company

• Golden Rules of ESD Due Diligence for Third
  Party Intellectual Property

By Rosario Consiglio, Impulse Semiconductor 2006
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Rule 1

• It is never too early to make ESD planning is
  part of your design flow.

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Frequent ESD Management Pitfalls

• Insufficient time is allowed for IP vendors to
  correct ESD oversights and errors
• Checking ESD after package design is frozen (big
  problem with flip-chip designs)
• Putting off an ESD review until after first
  silicon reveals a problem
• Putting off the first ESD review until just days
  before tape out

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Frequent ESD Problem Areas

• Low voltage I/O
• Low voltage PLL blocks
• High speed reference clock blocks
• 5 volt tolerant designs on using LV CMOS
• All analog IP without specifically designed I/O
• More than three power supply domains
• Power management circuits

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Rule 2

• The Wafer Foundry will never provide all the ESD
  support you need.

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Rule 2 Comments

• Wafer Foundry ESD expertise is usually weighted
  in device design rather than ESD applications
• Foundry application guidelines and datasheets
  only cover 1-2 basic applications (ESD NMOST,
  PMOST)
• Most Layout ESD and latchup rules are only
  checked manually
• CAD design rule checks, LVS do not include ESD
  checks
• Ask how the Foundry qualifies IP vendors

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Rule 3

• The Integrated ESD level for the whole IC is
  always less than the sum of its third party IP
  parts.

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Rule 3 Comments

• IP vendors may try, but cannot anticipate all ESD
  application problems with their products
• Independent IP providers judge ESD performance of
  their individual PHY based on their respective
  test chip results
• IP vender A will not guarantee their ESD
  circuits will protect IP from vendor B

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Hypothetical IC Layout Example
6000
2000
AFE section Vendor A
Digital I/O Vendor C
2K
7K
PLL Vendor E
Digital SRAM Core Vendor D
500
CLK SQR
500
4K
Digital I/O Vendor B
8000
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ESD Integration Issues

• Due to required pin combinations, certain ESD
  discharge paths may be very resistive
• Voltage drops on any particular path may be
  excessive
• ESD clamps from IP vendor A may be incompatible
  with IP from vendor B
• Insufficient isolation between IP block may
  result in excessive noise and Latchup

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Important IP ESD Information

• A test report indicating 2KV HBM, 200V MM, 500V
  CDM is helpful but insufficient by itself
• Know Pass diode resistance
• Knowledge of ESD clamp dynamic resistance or ESD
  clamping voltage for protection elements
• Know I/O cell metal layer composition, and number
  of squares to compute resistance
• Signal buffering/Pi network configuration

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Possible IC Power Domains
9 sq
32 sq
22 sq vdd
6.1 sq vdd
9 sq
6.1 sq vdd
3.2 sq
VDD is outer ring
2.2 sq vdd
clamp
28 sq vdd
41 sq
2.2 sq vdd
3.2 sq
clamp
VDD
17.5 sq vdd
28 sq vdd
25.6 sq
I/O
41 sq
VSS is the outer ring
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Modeling of Core Interconnect May be Necessary
for Accurate Estimates
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Rule 4

• Seek out test data, ask questions.

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Test Data From IP Vendors

• Independent Lab reports for HBM, MM, CDM results.
  
• Transmission line pulse I/V for ESD clamps
• ESD parameters extracted from TLP measurements
  for wafer foundry processes
• Latchup current values for different I/O types
  over temperature

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IP Provider ESD Design Queries

• ESD device clamping voltages at 1.5 amps/100ns
  is it compatible with wafer foundry ESD limits?
• Noise isolation techniques is the pass diode
  voltage drop less than wafer foundry technology
  limits?
• Is the metalization wide enough for low voltage
  drops?

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IP Provider Design Margins Queries continued

• Are there antenna diodes for internal buffers,
  supply lines and long signal paths?
• What analog signals are routed directly to I/O?
• What is the input Pi network?
• What foundry data used to design ESD structures?

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Foundry ESD/latchup parameters

• Secondary breakdown currents and voltages for ESD
  layouts
• Worst case Oxide breakdown statistics
• Resistor (poly, diffusion) current carrying
  capacities
• Metalization current carrying capacities
• Via, contact current carrrying capacities
• Does the Foundry have data from SEMATECH standard
  ESD evaluation structures?

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SEMATECH Foundry TLP Benchmarking Structures
Courtesy of Sematech