Designing a Single Cycle Datapath

1
Designing a Single Cycle Datapath

• In this lecture, slides from lectures 3, 8 and 9
  from the course Computer Architecture ECE 201 by
  Professor Mike Schulte are used with permission.

2
The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Todays Topic Design a Single Cycle Processor

3
The Big Picture The Performance Perspective

• Performance of a machine is determined by
• Instruction count
• Clock cycle time
• Clock cycles per instruction
• Processor design (datapath and control) will
  determine
• Clock cycle time
• Clock cycles per instruction
• Single cycle processor - one clock cycle per
  instruction
• Advantages Simple design, low CPI
• Disadvantages Long cycle time, which is limited
  by the slowest instruction.

4
How to Design a Processor step-by-step

• 1. Analyze instruction set gt datapath
  requirements
• the meaning of each instruction is given by
  register transfers
• Rrd lt Rrs Rrt
• datapath must include storage element for ISA
  registers
• datapath must support each register transfer
• 2. Select set of datapath components and
  establish clocking methodology
• 3. Design datapath to meet the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Design the control logic

5
MIPS Instruction set
6
Review The MIPS Instruction Formats

• All MIPS instructions are 32 bits long. The
  three instruction formats are
• R-type
• I-type
• J-type
• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination register
  specifiers
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

7
Translating MIPS Assembly into Machine Language

• Humans see instructions as words (assembly
  language), but the computer sees them as ones and
  zeros (machine language).
• An assembler translates from assembly language to
  machine language.
• For example, the MIPS instruction add t0, s1,
  s2 is translated as follows (see back of book)
• Assembly Comment
• add op 0, shamt 0, funct 32
• t0 rd 8
• s1 rs 17
• s2 rt 18

00000
100000
01000
10010
10001
000000
funct
shamt
rd
rt
rs
op
8
MIPS Addressing Modes

• Addressing modes specify where the data used by
  an instruction is located.
• mode example action
• register direct add s1, s2, s3 s1 s2
  s3
• immediate addi s1, s2, 200 s1 s2 200
• baseindex lw s1, 200(s2) s1 mem200
  s2
• PC-relative beq s1, s2, 200 if (s1 s2)
• PC PC42004
• Pseudo-direct j 4000 PC (PC3128, 40004)
• Often, the type of addressing mode depends on the
  type of operation being performed (e.g., branches
  all use PC relative)
• A summary of MIPS addressing modes is given on
  the back cover of the book.

9
MIPS Addressing Modes/Instruction Formats

• All MIPS instructions are 32 bits wide - fixed
  length

add s1, s2, s3
Register (direct)
op
rs
rt
rd
register
Immediate
addi s1, s2, 200
immed
op
rs
rt
Baseindex
immed
op
rs
rt
Memory
register

lw s1, 200(s2)
PC-relative
immed
op
rs
rt
Memory
PC

beq s1, s2, 200
10
Step 1a The MIPS Subset for Today

• ADD and SUB
• addu rd, rs, rt
• subu rd, rs, rt
• OR Immediate
• ori rt, rs, imm16
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16

11
Register Transfer Logic (RTL)

• RTL gives the meaning of the instructions
• All instructions start by fetching the instruction

op rs rt rd shamt funct MEM PC op
rs rt Imm16 MEM PC
inst Register Transfers addu Rrd lt Rrs
Rrt PC lt PC 4 subu Rrd lt Rrs
Rrt PC lt PC 4 ori Rrt lt Rrs
zero_ext(imm16) PC lt PC 4 load Rrt lt
MEM Rrs sign_ext(imm16) PC lt PC
4 store MEM Rrs sign_ext(imm16) lt
Rrt PC lt PC 4 beq if ( Rrs Rrt )
then PC lt PC 4 sign_ext(imm16) 00
else PC lt PC 4
12
Step 1 Requirements of the Instruction Set

• Memory
• instruction data
• Registers (32 x 32)
• read rs
• read rt
• write rt or rd
• PC
• Extender (sign extend or zero extend)
• Add and sub register or extended immediate
• Add 4 or shifted extended immediate to PC

13
Step 2 Components of the Datapath
CarryIn

• Adder
• MUX
• ALU

A
32
Sum
Adder
32
B
Carry
32
Select
A
32
Combinational LogicDoes not use a clock
Y
MUX
32
B
32
OP
3
A
32
Result
ALU
32
B
32
14
Storage Element Register (Basic Building Blocks)
Write Enable

• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write enable input
• Write Enable
• negated (0) Data Out will not change
• asserted (1) Data Out will become Data In on the
  falling edge of the clock

Data In
Data Out
N
N
Clk
15
Clocking Methodology - Negative Edge Triggered
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge
• Cycle Time CLK-to-Q Longest Delay Path
  Setup Clock Skew

16
Storage Element Register File
RW
RA
RB

• Register File consists of 32 registers
• Two 32-bit output busses
• busA and busB
• One 32-bit input bus busW
• Register is selected by
• RA (number) selects the register to put on busA
  (data)
• RB (number) selects the register to put on busB
  (data)
• RW (number) selects the register to be
  writtenvia busW (data) when Write Enable is 1
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a combinational
  logic block
• RA or RB valid gt busA or busB valid after
  access time.

Write Enable
5
5
5
busA
busW
32
32 32-bit Registers
32
busB
Clk
32
17
Register File - Read

• Built using D flip-flops

18
Register File - write
19
Storage Element Idealized Memory
Write Enable
Address

• Memory (idealized)
• One input bus Data In
• One output bus Data Out
• Memory word is selected by
• Address selects the word to put on Data Out
• Write Enable 1 address selects the memoryword
  to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, memory behaves as a
  combinational logic block
• Address valid gt Data Out valid after access
  time.

32
Data In
DataOut
32
32
Clk
20
Step 3

• Register Transfer Requirements gt Datapath
  Design
• Instruction Fetch
• Decode instructions and Read Operands
• Execute Operation
• Write back the result

21
3a Overview of the Instruction Fetch Unit

• The common RTL operations
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Instruction Word
32
22
3b Add Subtract

• Rrd lt- Rrs op Rrt Example addu rd,
  rs, rt
• Ra, Rb, and Rw come from instructions rs, rt,
  and rd fields
• ALUctr and RegWr control logic after decoding
  the instruction

Rs
Rt
Rd
ALUctr
RegWr
5
5
5
3
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
busB
Clk
32
23
3c Logical Operations with Immediate

• Rrt lt- Rrs op ZeroExtimm16 Example ori
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
3
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
ZeroExt
imm16
32
16
ALUSrc
24
3d Load Operations

• Rrt lt- MemRrs SignExtimm16
  Example lw rt, rs, imm16

Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
3
busA
W_Src
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
MemWr
32
Mux
Mux
WrEn
Adr
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc
ExtOp
25
3e Store Operations

• Mem Rrs SignExtimm16 lt- Rrt Example
  sw rt, rs, imm16

Rt
Rd
ALUctr
MemWr
W_Src
RegDst
Mux
3
Rs
Rt
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
Mux
WrEn
Adr
Data In
32
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
26
3f The Branch Instruction

• beq rs, rt, imm16
• memPC Fetch the instruction from memory
• Equal lt- Rrs Rrt Calculate the branch
  condition
• if (COND eq 0) Calculate the next instructions
  address
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• else
• PC lt- PC 4

27
Datapath for Branch Operations

• beq rs, rt, imm16 Datapath generates
  condition (equal)

Inst Address
nPC_sel
32
00
imm16
PC Ext
28
Putting it All Together A Single Cycle Datapath
Instructionlt310gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Equal
Rt
Rd
3
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb

busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
Clk
1
Data In
Extender
Data Memory
imm16
PC Ext
32
16
imm16
Clk
ExtOp
ALUSrc
29
Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt05gt
lt2631gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
nPC_sel
ALUSrc
RegDst
ExtOp
RegWr
Equal
DATA PATH
30
A Single Cycle Datapath

• We have everything except control signals
  (underlined)
• Todays lecture will look at how to generate the
  control signals

31
Meaning of the Control Signals

• MemWr write memory
• MemtoReg 0 gt ALU 1 gt Mem
• RegDst 0 gt rt 1 gt rd
• RegWr write dest register

• ExtOp zero, sign
• ALUsrc 0 gt regB 1 gt immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
3
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Extender
Data Memory
imm16
32
16
Clk
ExtOp
ALUSrc
32
RTL The Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

33
The Single Cycle Datapath during Add/Sub

• Rrd lt- Rrs op Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 1
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
34
Instruction Fetch Unit at the End of Add

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

Instructionlt310gt
nPC_sel 4
4
00
PC
Clk
imm16
35
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
36
The Single Cycle Datapath during Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
37
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
32
1
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
38
The Single Cycle Datapath during Branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

Instructionlt310gt
nPC_sel Br
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Subtract
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
39
Instruction Fetch Unit at the End of Branch

• if (Zero 1) then PC PC 4
  SignExtimm164
• else PC PC 4

Instructionlt310gt
nPC_sel
See book for what the datapath and control looks
like for jump instructions. Compared to book our
processor also supports the ORI instructions.
4
00
PC
Clk
imm16
40
A Summary of the Control Signals
func
10 0000
See
10 0010
We Dont Care -)
Appendix A
op
00 0000
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
add, sub
I-type
ori, lw, sw, beq
J-type
jump
41
Step 5 The Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
42
The Encoding of ALUop

• In this exercise, ALUop has to be N2 bits wide
  to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop has to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract (5) And (6) Set
  on lt

R-type
ori
lw
sw
beq
jump
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUoplt20gt
1 00
0 10
0 00
0 00
xxx
0 01
43
The Decoding of the func Field
Our processor only implements subset of operations
Get func from back of book for R-type
44
The Truth Table for ALUctrlt2gt
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
This control is for more R-type instructions than
our processor, but fewer than the entire MIPS
ISA.
45
The Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt funclt1gt

46
The Truth Table for ALUctr lt1gt
47
The Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt funclt2gt

48
The Truth Table for ALUctrlt0gt
49
The Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt 2gt funclt2gt funclt0gt
• ALUoplt2gt funclt3gt

50
The ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt funclt1gt

• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt funclt2gt

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt 2gt funclt2gt funclt0gt
• ALUoplt2gt funclt3gt

51
The Truth Table for the Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
Branch
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
52
The Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
0
0
0

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
53
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
54
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
6
Instrlt50gt
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
55
An abstract view of the critical path - load
instruction
Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Worst case delay for load is much longer than
needed for all other instructions, yet this sets
the cycle time.
56
An Abstract View of the Implementation
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Datapath

• Logical vs. Physical Structure

57
Summary

• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Design datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Design the control logic
• MIPS makes it easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
• Single cycle datapath gt CPI1, CCT gt long
• Next time implementing control