IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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IEEE Bipolar/BiCMOS Circuits and Technology
Meeting
Ultra High Frequency Static Dividers gt 150 GHz in
a Narrow Mesa InGaAs/InP DHBT Technology
Zach Griffith, Mattias Dahlström, and Mark J.W.
Rodwell Department of Electrical and Computer
Engineering University of California, Santa
Barbara, CA, USA Miguel Urteaga, Richard
Pierson, Petra Rowell, and Bobby Brar Rockwell
Scientific Corporation, Thousand Oaks, CA,
USA Sangmin Lee, Nguyen Nguyen, and Chanh
Nguyen Global Communication Semiconductors,
Torrance, CA, USA griffith_at_ece.ucsb.edu,
805-893-3273, 805-893-3262 fax
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Motivation for InP HBTs
Parameter InP/InGaAs Si/SiGe benefit
(simplified) collector electron velocity 3E7
cm/s 1E7 cm/s lower tc , higher Jbase electron
diffusivity 40 cm2/s 2-4 cm2/s lower tbbase
sheet resistivity 500 Ohm 5000 Ohm lower
Rbbcomparable breakdown fields Consequences, if
comparable scaling parasitic reduction 31
higher bandwidth at a given scaling
generation31 higher breakdown at a given
bandwidth Problems for InP HBTs SiGe has much
better scaling parasitic reduction Present
efforts in InP HBT research community
Development of low-parasitic, highly-scaled,
high-yield fabrication processes Why mesa
DHBT?Simple way to continue the advance of
epitaxial material for improved speed
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High speed HBT some standard figures of merit

• Small signal current gain cut-off frequency (from
  H21)
• Power gain cut-off frequency (from U)

Collector capacitance charging time when
switching
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Why Static Frequency Dividers ?

• MS flip-flops are very widely-used high speed
  digital circuits
• Master-Slave Flip-Flop with inverting feedback
• Connection as 21 frequency divider provides
  simple test method
• Standard benchmark of logic speed
• Performance comparisons across technologies
• Dynamic, super-dynamic, frequency dividers
• Higher maximum frequency than true static
  dividers
• Narrow-band operation ? applications are
  limited
• High Speed technology performance
• UCSB / RSC / GCS 152 GHz static divider using
  InGaAs/InP mesa DHBT
• IBM 96 GHz static divider using advanced mesa
  Si/SiGe HBT

A. Rylyakov, T. Zwick, IEEE GaAsIC Symposium, 2003
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Divide-by-2 versus Divide-by-4

• Divide-by-2
• latch with feedback
• 300 mVpp buffer, 50 Ohm loading
• easily tested with sampling scope or
  spectrum analyzer
• Divide-by-4
• 2 stages
• interstage buffer has 25 Ohm loading
• easily tested with sampling scope or
  spectrum analyzer

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How do we make HBTs faster
What we improved at the device level to increase
this generation of ckt speed
key device parameter required changes to double bandwidth
collector depletion layer thickness decrease 21
base thickness decrease 0.7071
emitter junction width decrease 41
collector junction width decrease 41
emitter resistance per unit emitter area decrease 41
current density increase 41
base contact resistivity (if contacts lie above collector junction) decrease 41
base contact resistivity (if contacts do not lie above collector junction) unchanged
Reduced from 200 nm to 150 nm
Reduced from 0.7 ?m to 0.5 ?m
Reduced from 30 to 20 ???m2
Increased by factor 2.5
(C s, t s, C/I s all reduced 21)
easily derived from geometry / resistivity /
velocity relationships
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DHBT Layer Structure for high f? and digital ckts
Vbe 0.75 V, Vce 1.3 V
Emitter
Collector
Base

• Compared to previous UCSB mesa HBT results
• Thinner InP collectordecrease ?c
• Collector doping increasedincrease JKirk
• Thinner InGaAs in subcollectorremove heat
• Thicker InP subcollectordecrease Rc,sheet

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Mesa DHBTs with 150 nm collector
0.6 x 7 mm2 emitter junction 15 W-mm2 contact
resistivity
30 nm InGaAs base 8?1019/cm3?5?1019/cm3
grade 603 W/square 0.5 mm wide base
contacts 20 W-mm2 contact resistivity
150 nm collector 20 nm InGaAs setback layer 24
nm InGaAlAs superlattice grade 103 nm InP
remaining thickness 0.2 mm collector undercut
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RF performancerecord f?, high fmax, and low
Ccb/Ic
Griffith et al, IEEE Electron Device LettersMay
2004
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Device modeling of transistor
Details of device parasitics
?collector ? 3.5?107 cm/sec, Vturn-on 0.9 V
?cont and ?sheet measured from TLMs
Ccb calculated from particular device dimensions
Withdrawn from device, added externally
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Fast divider designdesign considerations
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Why isn't basecollector transit time so
important for logic?
Depletion capacitances present over full voltage
swing, no large-signal reduction
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Fast divider designdevice considerations
Collector Field Collapse (Kirk Effect)
Collector Depletion Layer Collapse
Collector capacitance charging time scales
linearly with collector thickness if J Jmax
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Key HBT Scaling Limit ? Emitter Resistance
ECL delay not well correlated with f? or fmax
Largest delay is charging Ccb
? Je ? 10 mA/?m2 needed for 200 GHz clock rate
Voltage drop of emitter resistance becomes
excessive RexIc ?exJe (15 ???m2) ? (10
mA/?m2) 150 mV ? considerable fraction of
?Vlogic ? 300 mV Degrades logic noise margin
? ?ex ? 7 ???m2 needed for 200 GHz clock rate
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Trade-offs between interconnect wiring
environments
CPW has parasitic modes, coupling from poor
ground plane integrity
V
0V
V
V
V
0V
0V
0V
Microstrip mode
Substrate modes
CPW mode
-- ground straps suppress slot mode, but
multiple ground breaks in compex ICs produce
ground return inductance -- ground vias suppress
microstrip mode, wafer thinning suppresses
substrate modes
Microstrip wiring has
kz
high via inductance
has mode coupling unless substrate is thin
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Thin-film microstrip wiring, inverted is best for
complex ICs
Divider before ground plane deposition
Divider after ground plane deposition
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Design approach for fast logic

• Objective
• Design a divider to operate at ? 150 GHz
• UCSBs approachhow to get to 150 GHz
• Employ single level ECL for the data and clk
  level on both the acquire and hold sections of
  divider
• Microstrip wiring environment with low loss ?r
  2.7
• Minimize (DVlogicCcb/Ic ) loading
• Use small devices operating at high
• current density
• Add small peaking inductance to data bus to
  shorten data transition time
• Simulated results with distributed device model
• Maximum frequency divider speed ? 168 GHz

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UCSB DHBTs withstand ECL voltageswhen biased at
the currents needed for speed
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Layout and simulated performance
Simulated divider speed w/ TFAST device model Tc
150 nm, Tb 40 nm Rex,cont ? 30 ???m2, Rbb,
cont ? 20 ???m2 Resistive pulldown only RLoad
45 ?, fmax 122 GHz RLoad 35 ?, fmax 129
GHz RLoad 25 ?, fmax 133 GHz w/ Inductive
peaking 62 pH RLoad 45 ?, fmax 136
GHz RLoad 35 ?, fmax 150 GHz RLoad 25 ?,
fmax 168 GHz
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Precise Details of 150 GHz UCSB/RSC/GCS divider
units data current steering data emitter followers clock current steering clock emitter followers
size mm2 0.5 x 4 0.5 x 5 0.5 x 5 0.5 x 6
currentdensity mA/mm2 6.0 4.0 4.8 3.3
Ccb/Ic ps / V 0.59 0.99 0.59 0.86
Vcb V 0.6 0 0.6 1.7
ft GHz 301 260 301 280
fmax GHz 358 268 358 280

• Key features in the divider design
• Circuit topologyemitter coupled logic (ECL)
• inductive peaking 62 pH
• no clock input buffer usedsingle ended clk
  drive
• power dissipation, divider core only 594.7 mW
• power dissipation, w/ output buffer 659.1 mW
• devices sized to either operate at
• JKirk for minimum Ccb/Ic ratio
• sizes large enough where IE?Rex potential
  drops are not a significant portion of ?Vlogic

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Low frequency clocking and sensitivity of 150 GHz
divider
Output waveform _at_ 1.5 GHz, fclk 3 GHz
Variation of input sensitivity with frequency

• The divider is operational from 152 GHz down to
  3 GHz at identical DC bias conditions
• this confirms the circuit is fully static
• The sensitivity plot shows a divider
  self-oscillation frequency of 87 GHz

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UCSB/RSC/GCS static divide-by-2 circuit at 152
GHz
Span DC to 77 GHz
Span 5 MHz
Measurements performed at Mayo with RSC and UCSB
Participation RSC Wafer GCS12-005, Divider ID
R3C4 48, Fabricated at GCS, Design at UCSB VDI
Source Used For CLK Input, Vclk offset ? -1.7 V,
VEE -4.07 V, IEE 162.1mA, PDC,total 659.8
mW Power dissipation of divider core without
output buffer ? 594.7 mWtested at room temp
(25?C)
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UCSB/RSC/GCS static divide-by-4 circuit at 137
GHz
Span DC to 50 GHz
Span 100 MHz
Measurements performed at UCSB, GUNN Source Used
For CLK Input RSC Wafer GCS12-005, Divider ID
R3C4 48, Fabricated at GCS, Design at UCSB Vclk
offset ? -1.7 V, VEE, div2 -4.10 V, IEE, div2
159.9 mA, VEE, div4 -4.20 V, IEE, div4 118.5
mA Power dissipation of divider core without
output buffer ? 587.6 mWtested at room temp
(25?C)
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142 GHz divide by 2--fabricated at UCSB Nanofab
Bias conditions Ptotal 888.3 mW Pcore ? 800
mW Iee 210 mA Vee -4.23 V fclk,min 3 GHz
Span DC to 75 GHz
Span 5 MHz
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UCSB/RSC/GCS static divide-by-2 circuit temp
comparison
RSC Wafer GCS12-005, Divider ID R3C4 48
fclk 150 GHz, Pout -35.8 dBm
fclk 152 GHz, Pout -44.5 dBm
fclk 153 GHz, Pout -37.3 dBm
Wafer chuck temperature _at_ 25?C
Wafer chuck temperature _at_ 20?C

• Dividers are not being minimum gate delay
  limited they are being thermally limited by
  the input clock devices
• Because of device operating conditions for the
  clock input devices (Vce ? 2.6 V, Je ? 5
  mA/?m2, P ? 13 mW/?m2), they get hot
• Moderate cooling needed in order to
  improve/increase circuit performance

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Conclusion

• Static frequency dividers measured to a high fclk
  152 GHz
• Circuit performance increased by doing the
  following
• Emitter coupled logic (ECL) topology and peaking
  inductance
• Reduced collector thickness, 150 nm
• Device operation at JKirk for respective Vcb
• Reduced base-collector mesa area, Ac / Ae ? 3.0
• Microstrip wiring environment for well behaved
  impedance at gt 100 GHz
• Continued reduction of device parasitics needed
  for improved speed
• Collector needs to be thinned because
  Ccb?VLogic / Ic ? Tc _at_ Je JKirk
• But Rex consumes portions of logic swing as
  Ie?Rex ? Je??e ? Tc-2
• Collector pedestal needed for improved speed and
  reduced power
• Reduced Ccb / Ic for improved speed, Constant Ccb
  / Ic for reduced power

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Conclusion
Thank you
Acknowledgements This work was supported under
by DARPA under the TFAST programN66001-02-C-8080