Synchronization of complex systems

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Synchronization ofcomplex systems

• Jordi Cortadella
• Universitat Politecnica de Catalunya
• Barcelona, Spain

Thanks to A. Chakraborty, T. Chelcea,M.
Greenstreet and S. Nowick
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Multiple clock domains
CLK1
f1/f0
CLK (f0)
f2/f0
CLK2
CLK0
CLK
f3/f0
CLK3
Independent clocks (plesiochronousif
frequenciesclosely match)
Single clock (Mesochronous)
Rational clock frequencies
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The problem metastability
D
Q
D
Q
?T
?R
?R
setup
hold
D
Q
?
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Classical synchronous solution
?T
?R
Example
Mean Time Between Failures f? frequency of
the clock fD frequency of the data
tr resolve time available W metastability
window ? resolve time constant
FFs MTBF
1 FF 15 min
2 FF 9 days
3 FF 23 years
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How to live with metastability ?

• Metastability cannot be avoided, it must be
  tolerated.
• Having a decent MTBF (? years) may result in
  atangible impact in latency
• Purely asynchronous systems can be
  designedfailure-free
• Synchronous and mixed synchronous-asynchronous
  systems need mechanisms with impact in latency
• But latency can be hidden in many cases

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Different approaches

• Pausible Clocks (Yun Donohue 1996)
• Predict metastability-free transmission windows
  for domains with related clocks (Chakraborty
  Greenstreet 2003)
• Use the waiting time in FIFOs to resolve
  metastability(Chelcea Nowick 2001)
• And others
• The term Globally Asynchronous, Locally
  Synchronous is typically used for these systems
  (Chapiro 1984)

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Mutual exclusion element
0
ack1
req1
1
0
req2
1
0
ack2
0
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Mutual exclusion element
Metastability resolver
0
1
0
ack2
req1
req2
ack1
1
0
0
An asynchronous data latch with MS resolver can
be built similarly
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Abstraction of the MUTEX
R1
G1
MUTEX
R2
G2
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A pausible clock generator
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Pausible clocks
Req
Ack
FF
ME
MUTEX
d1, d2
CLK
Yun Dooply, IEEE Trans. VLSI, Dec. 1999 Moore
et al., ASYNC 2002
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STARI (Self-Timed At Receivers Input)

• Both clocks are generated from the same source
• The FIFO compensates for skew between transmitter
  and receiver
• M. Greenstreet, 1993

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A Minimalist Interface

• FIFO reduces to latch-X and a latch controller
• Fx can always be generated in such a way as to
  reliably transfer data from input to output
• Chakraborty Greenstreet, 2002

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A Minimalist Interface 3 scenarios
Latch-X setup hold
Latch-R setup hold
?x Permitted
The scenario is chosenat initialization
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A Minimalist Interface latch controller
The controller detects which transition arrives
first (from FT and FR) and generates FX
accordingly
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A Minimalist Interface rational clocks
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A Minimalist Interface arbitrary clocks

• Assumption clocks are stable
• Each domain estimates the others frequency
• Residual error corrected using stuff bits

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Mixed-Timing Interfaces
Async-Sync FIFO
Async-Sync FIFO
Sync-Async FIFO
Mixed-Clock FIFOs
Chelcea Nowick, 2001
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Mixed-Clock FIFO Block Level
full
req_get
valid_get
req_put
Mixed-Clock FIFO
synchronous get interface
synchronous put inteface
empty
data_put
data_get
CLK_put
CLK_get
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Mixed-Clock FIFO Block Level
Initiates put operations
Initiates get operations
Bus for data items
Bus for data items
full
req_get
valid_get
req_put
Mixed-Clock FIFO
synchronous get interface
synchronous put inteface
empty
data_put
data_get
CLK_put
CLK_get
Controls put operations
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Mixed-Clock FIFO Block Level
Indicates data items validity (always 1 in this
design)
Indicates when FIFO full
full
req_get
valid_get
req_put
Mixed-Clock FIFO
synchronous get interface
synchronous put inteface
empty
data_put
data_get
CLK_put
CLK_get
Indicates when FIFO empty
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Mixed-Clock FIFO Architecture
full
Full Detector
req_put
Put Controller
data_put
CLK_put
CLK_get
data_get
req_get
Get Controller
valid_get
Empty Detector
empty
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Mixed-Clock FIFO Cell Implementation
CLK_put
en_put
req_put
data_put
ptok_out
ptok_in
f_i
REG
e_i
gtok_in
gtok_out
CLK_get
en_get
valid
data_get
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Mixed-Clock FIFO Cell Implementation
CLK_put
req_put
en_put
data_put
ptok_out
ptok_in
PUT INTERFACE
f_i
REG
e_i
GET INTERFACE
gtok_in
gtok_out
data_get
CLK_get
en_get
valid
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Synchronization summary

• Resolving metastability implies latency
• Latency can be often hidden (FIFOs, Chelcea
  Nowick)
• Clock frequencies can be estimated and clock
  edges predicted under the assumption of stable
  clocks (Chakraborty Greenstreet)
• Pausible clocks are also possible (Yun Donohue
  1996)
• But still the nicest solutions are totally
  asynchronous
• As presented by Fulcrum Microsystems in the last
  lecture