Using Partial Implications for Redundancy Identification and Fault Equivalence PowerPoint PPT Presentation

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Title: Using Partial Implications for Redundancy Identification and Fault Equivalence


1
Using Partial Implications for Redundancy
Identification and Fault Equivalence
  • Vishwani D. Agrawal
  • Agere Systems, Murray Hill, New Jersey
  • va_at_agere.com
  • http//cm.bell-labs.com/cm/cs/who/va

2
Talk Outline
  • Problem statement
  • Background
  • Implication graph
  • Partial implications
  • Transitive closure
  • Redundancy identification
  • A new method for fault equivalence
  • Conclusion

3
Problem Statement
  • Many problems can be solved by implication graphs
    and transitive closure.
  • We will study two problems
  • Redundancy identification
  • Fault equivalence

4
Background
  • Implication graphs
  • Chakradhar, et al., Book90
  • Larrabee, IEEE-TCAD92
  • Transitive closure
  • ATPG Chakradhar, et al., IEEE-TCAD93
  • Redundancy, Agrawal, et al., ATS96
  • Partial implications
  • Henftling, et al., EDAC95
  • Gaur, et al., DELTA02, Gaur, MS Thesis02
  • Fault equivalence
  • Bushnell and Agrawal, Book00

5
Implication graph
An implication graph is a representation of
logical implications between pairs of signals of
a digital circuit.
  • Nodes
  • Two nodes per signal nodes a and a correspond to
    signal a.
  • A node has two states (true,false) represents
    the signal state.
  • Edges
  • A directed edge from node a to b means a1
    implies b1.

6
Building an Implication Graph
A B
B
C
A
C
AB C 0
A
B
C
AC BC ABC 0
  • If C is 1 then that implies that A and B must
    be 1, but the reverse is not true. Similarly,
    if either A or B is 0 then C will be 0. But
    if we want to represent the implications of A and
    B on C then partial implications are necessary.

7
Partial Implications
A B
B
C
A
C
AB C 0
A
B
C
AC BC ABC 0

Reference Henftling, et al., EDAC, 1995
8
Observability Variables
  • Observability variable of a signal represents
    whether or not that signal is observable at a PO.
    It can be true or false.

OA
OC 1
OC
A B
OA
C
B
(PO)
OB
OCB OA 0
OCOA BOA OCBOA 0
9
Adding Observability Variables to Implication
Graph
OC

OA
OCOA BOA OCBOA 0
B
OA
OC
B
C
A
OC
OA
A
B
C
OB can be added similarly.
10
Transitive Closure
  • Transitive closure of a directed graph contains
    the same set of nodes as the original graph.
  • If there is a directed path from node a to b,
    then the transitive closure contains an edge from
    a to b.

a
b
a
b
c
c
d
d
Transitive closure
A graph
11
Stuck-at Faults
  • This is a type of fault, which causes a line to
    hold a constant logic value, irrespective of
    change of state at previous stages.
  • There are two types of stuck-at-faults
  • Stuck-at-1
  • Stuck-at-0
  • Detection of a fault requires the fault to be
    activated and its effect observable at a PO.
  • Fault a s-a-1 is detectable, iff following
    conditions can be simultaneously satisfied
  • a 0
  • Oa 1

12
Redundant Faults
  • A fault that has no test is called an untestable
    fault.
  • Any untestable fault in a combinational circuit
    is a redundant fault because it does not cause
    any change in the input/output logic function of
    the circuit.
  • Identification of redundant faults is useful
    because they can be removed
  • from testing consideration, or
  • from hardware

13
Redundancy Identification
  • ATPG based method
  • It uses exhaustive test pattern generation to
    determine whether or not a target fault has a
    test.
  • All redundant faults can be found, but the ATPG
    cost is high (exponential in circuit size).
  • Fault independent method
  • This method analyzes circuit topology and
    function locally without targeting a specific
    fault.
  • Many (not all) redundant faults can be found at a
    lower cost.

14
Redundancy Identification by Transitive Closure
b
c
a
d
c
a
s-a-0
e
s-a-0
b
Od
Oc
d
Circuit with two redundant faults
Implication graph (some nodes and edges not shown)
Implication Partial implication Transitive
closure edge
15
Method Summarized
  • Obtain an implication graph from the circuit
    topology and compute transitive closure.
  • Examine all nodes
  • S-a-0 is redundant if the signal implies its
    complement.
  • S-a-1 is redundant if the complement of the
    signal implies the signal.
  • Both faults are redundant if the signal and its
    complement imply each other.
  • S-a-0 is redundant if the signal implies its
    false observability variable.
  • S-a-1 is redundant if the complement of the
    signal implies its false observability variable.
  • S-a-0 is redundant if the observability variable
    implies the complement of the signal.
  • S-a-1 is redundant if the observability variable
    implies the signal.
  • Both faults are redundant if the observability
    variable and its complement imply each other.

16
Classification of Redundant Faults by TCAND
HITEC, Nierman and Patel, EDAC91
17
Complexity of TCAND
SUN Sparc 5
18
Limitation of Method
  • Observability variable of a fanout stem is not
    analyzed.
  • Only the redundant faults due to false
    controllability of fanout stem can be identified.

s-a-1
s-a-0
Three redundant s-a-0 faults identified
by transitive closure
Two redundant stem faults not identified by
transitive closure
19
Some Conclusions
  • Partial implications help find more redundant
    faults than the transitive closure without
    partial implications.
  • The results have been compared with FIRE (another
    fault-independent program), which did equal to or
    worse that transitive closure with partial
    implication.
  • Transitive closure computation run times were
    linear in the number of nodes for the implication
    graphs of benchmark circuits, although the known
    worst-case complexity is O(N3) for N nodes.

20
Fault Equivalence
  • Two faults of a Boolean circuit are called
    equivalent if they transform the circuit such
    that the two faulty circuits have identical
    output functions.
  • Equivalent faults are indistinguishable and have
    exactly the same set of tests.
  • Many fault equivalences can be determined by
    structural analysis based on gate fault
    equivalences and circuit interconnects this is
    done in practice.
  • Some fault equivalences require equivalence
    checking of faulty circuits too complex and not
    generally done.

21
Gate Fault Equivalence
sa1
sa0
sa0
sa1
sa1
sa0
sa1
sa0
sa1
sa0
sa1
sa0
sa0
sa1
sa1
sa0
sa0
sa0
sa0
sa1
sa0
sa1
sa1
sa1
sa1
sa0
22
Sa0 and Sa1 Variables
Variable Asa0 assumes a true state when A1 and
OA is true
s-a-0
A
A B
Asa0
C
OA
Asa1 is similarly defined.
23
Equivalence by Imp. Graph
s-a-0
s-a-0
A
C
Asa0
Csa0
B
OA
OC
B
C
A
OC
OA
A
B
C
24
An Open Question
  • Can implication graph/transitive closure
    recognize functional fault equivalence. These
    are not found by structural analysis.
  • Example e b, for both faults.

s-a-1
a
e
s-a-1
b
25
Conclusion
  • Partial implications improve redundancy
    identification.
  • Present limitation of the method is the
    identification of redundancy due to the false
    observability of fanout stem open problem.
  • New formulation of fault equivalence may find
    some functional equivalences.

26
  • THANK YOU
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