ST7 MICROCONTROLLER TRAINING

1
ST7 MICROCONTROLLER TRAINING
1 - INTRODUCTION 2 - CORE 3 - ADRESSING MODES 4
- PERIPHERALS 5 - ST7 SOFTWARE TOOLS 6 - ST7
HARDWARE TOOLS 7 - STVD7
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ST7 I/O PORTS

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

3
ST7 I/O PORTSOverview

• ALL THE I/Os ARE INDIVIDUALLY SOFTWARE
  CONFIGURABLE USING 3 DIFFERENT REGISTERS
• DDR Data Direction Register
• DR Data Register
• OR Option Register
• ST72254 22 MULTIFUNCTION BIDIRECTIONAL I/O
  LINES
• 18 Standard I/Os (sink up to 5mA)
• 8 High Current I/Os (PA0-PA7 can sink up to 20mA)
• 6 Analog Inputs (PC0-PC5)
• 16 alternate Functions on 16 pins (for Timers,
  SPI and I2C)
• All the I/Os can be set-up as Interrupt inputs

4
ST7 I/O PORTSafe I/O pin transition
DDR OR Mode
0 0 Floating input
0 1 Input pull- up with/without interrupt
1 0 Output Open-Drain
1 1 Output Push-Pull
01
00
10
11
Reset State
5
ST7 I/O PORT Basic structure
Read / Write DDRi
Data Direction Register Bit
I/O Pin
Latch Data Output bit
Ouput
Input Reg bit
Input I/O
6
ST7 I/O PORT Settings electrical behaviour

• Configuration given when no external Hardware is
  connected the pins

InputFloating InputFloating Input Pull_up Input Pull_up Ouput Open Drain Ouput Open Drain OuputPush-Pull OuputPush-Pull
DDR 0 0 0 0 1 1 1 1
OR 0 0 1 1 0 0 1 1
Written DR 0 1 0 1 0 1 0 1
I/O Pin Floating Floating Vdd Vdd Vss Floating Vss Vdd
Read DR X X 1 1 0 1 0 1
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ST7 EXTERNAL INTERRUPTS
Pin 1
Interrupt Source 1
ST7 Interrupt Controller
Pin 2
Edge/level selection
Pin M
Pin 1
Interrupt Source 2
Pin 2
Edge/level selection
Pin N
Miscellaneous Register
Pin 1
Pin 2
Interrupt generation
Interrupt source
Negative edge only
Latched
Positive edge only
Latched
Negative edge and low level
Not Latched
Positive and Negative edge
Latched
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ST7 I/O PORT Block Diagram
Output Stage
ALTERNATE OUTPUT
1
0
ALTERNATE ENABLE
DR
DDR
PULL-UP
PAD
Condition
OR
DATA BUS
OR SEL
DDR SEL
DR SEL
1
0
ANALOG INPUT
ALTERNATE INPUT
EXTERNAL INTERRUPT SOURCE
FROM OTHER BITS
POLARITY SELECTION
Input Stage
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PROGRAMMING TIPSI/O Port (1)

• AD CONVERTION
• Each pin used by the ADC cell must be configured
  as floating input (i.e. without pull-up
  resistors) before activating the analog input
  mode
• ALTERNATE FUNCTION
• A signal coming from an on-chip peripheral can be
  output on a port. In this case, the I/O is
  automatically configured in output mode.
• A signal coming from an I/O can be an input to an
  on-chip peripheral. In this case, it must be
  configured as Input without interrupt (Floating
  Input).

10
PROGRAMMING TIPSI/O Port (2)

• Open Drain Outputs can be used for bus driving
  where several devices are connected on the same
  line. They can be wired together to increase
  current drive capability
• Voltages driving an Analog Input should always
  stay within the absolute maximum ratings
  (Vss-0.3V to Vdd0.3V)
• Pull-up resistors typically deliver 50µA under
  5V
• The toggling time on any output pin will be
  approximately 30ns for a 50pF load

11
I/O Ports Configuration Example

• Fill the dedicated I/O port registers in order to
  have the following configuration
• PB0PB2
• Push-Pull Output (high level)
• PB3,PB4
• Floating Input
• PB5
• Input with Interrupt
• PB6
• Push-Pull Output (low level)
• PB7
• Ouput (High Impedance)

PBDR0
PBDR7

PBDR
PBDDR7
PBDDR0

PBDDR
PBOR0
PBOR7

PBOR
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A/D CONVERTER

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

13
ST7 AD CONVERTEROverview (1)

• 8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP
  TO 8 ANALOG CHANNELS
• ST72254 6 inputs
• ST72334 and ST725xx 8 inputs
• ST72171 6 external inputs 2 internal inputs
• FEATURE
• Accuracy 1 LSB
• Total Unajusted Error MAX 1 LSB
• Conversion time 24 CPU cycle ie 3µs at full
  speed (8MHz)
• FLAGS
• COCO end of conversion (Status flag)
• ADON ADC on/off bit (to reduce power
  consumption)

14
ST7 AD CONVERTEROverview (2)

• LOW CONSUMPTION MODES
• Wait mode doesn't affect the ADC
• Halt mode stops the ADC.
• HARDWARE
• ST72334 and ST725xx Vdda and Vssa must be
  connected externally respectivelly to Vdd and Vss
  through decoupling capacitors.
• ST72254 connection done internally
• RATIONETRIC In the Functionnal Range
• If analog voltage input gt Vdd converted result
  FFh (no overflow indication)
• If analog voltage input lt Vss converted result
  00h (no underflow indication)

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ST7 AD CONVERTERBlock diagram
0
COCO
CH0
CH1
CH2
-
-
ADON
(Control Status Register) CSR
AIN0
AIN1
AIN2
SAMPLE
ANALOG
AIN3

ANALOG TO
MUX
AIN4
HOLD
DIGITAL
AIN5
CONVERTER
AIN6
AIN7
Fcpu
AD7
AD0
AD1
AD2
AD3
AD6
AD5
AD4
(Data Register) DR
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PROGRAMMING TIPSAD Converter

• PROCEDURE
• Step 1 The analog input pins must be set-up as
  Input no pull-up no interrupt
• Step 3 assign a channel for the conversion (bit
  CH0, CH1 and CH2 in CSR register) and set the
  ADON bit
• Step 4 Wait until COCO bit set. A continuous
  conversion is performed.
• To reach the best accuracy, the impedance seen by
  the analog input pin must be lower than 10Kohm.

17
ADC Configuration Example

• Fill ADCCSR register in order to have an analog
  conversion on AIN4.
• What bit has to be tested to know the end of the
  conversion ?

COCO ADON CH3 CH2 CH1 CH0
ADCDR

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ST7 16-bit TIMER

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

19
16-bit TIMEROverview (1)

• 16-bit free running counter driven by a software
  configurable prescaler
• 4 different modes
• Input capture (2 pins) to latch the value of
  the counter after a transition on the ICAPi pin
• Output compares (2 pins) to control an output
  waveform or to indicate when a period of time is
  over
• One pulse generation of a pulse when an
  external event occurs
• PWM generation of a signal with frequency and
  pulse length set by software (OCR1 and OCR2)

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16-bit TIMEROverview (2)

• The timer clock can be provided by
• The internal clock with a configurable ratio
• An external source Fext must 4 times slower
  than the internal clock (ie Fmax2Mhz)

CC1 CC0 Timer clock
0 0 Fcpu/4
0 1 Fcpu/2
1 0 Fcpu/8
1 1 External
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16-bit TIMER Block diagram
ST7 INTERNAL BUS
MCU-PERIPHERAL INTERFACE
8
CPU CLOCK
8-BIT BUFFER
LOW BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
EXEDG
16-BIT FREE RUNNING COUNTER
1/2 1/4 1/8
COUNTER ALTERNATE REGISTER
16
EXCLK
16
16
EDGE DETECT CIRCUIT 2
CC1
CC0
16-Bit INTERNAL TIMER BUS
ICAP1
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT 1
OVERFLOW DETECT CIRCUIT
ICAP2
LATCH 1
OCMP1
STATUS REGISTER
LATCH 2
OCMP2
OC1E
OC2E
OPM
EXEDG
CC1
PWM
CC0
IEDG2
CONTROL REGISTER 1
CONTROL REGISTER 2
TIMER INTERNAL INTERRUPT
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16-bit TIMERInput capture (1)

• Captures the counter value upon input signal edge
  detection
• Allows an external pulse length measurement
• Internal safety process in case of critical
  interrupts timing

Timer Counter Register
Input Capture Register
Edge Detector
ICAP1A
Software Maskable Interrupt Request
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16-bit TIMERInput capture (1)
ICAP1
(Control Register 1)
CR1
EDGE DETECT
EDGE DETECT
ICIE
IEDG1
ICAP2
CIRCUIT2
CIRCUIT1
(Status Register)
SR

ICF2
ICF1
0
0
0
IC1R
IC2R
(Control Register 2)
CR2

16-BIT
16-BIT
FREE RUNNING
CC0
CC1
IEDG2
COUNTER
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16-bit TIMEROuput compare (1)

• Event generation (Interrupt request/bit toggling)
  whenever the compare register matches the
  counter
• Indicates a period of time has elapsed and
  controls an output waveform
• Internal safety process in case of critical
  interrupts timing

Timer Counter Register
Software Maskable Interrupt Request Pulse
generation
Match?
Output Compare Register
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16-bit TIMEROutput compare (2)
16-BIT
FREE RUNNING
OC1E
CC0
CC1
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
Latch
OLVL1
OLVL2
OCIE
OCMP1
CIRCUIT
1
Latch
OCMP2
2
16-bit
16-bit
0
0
0
OCF2
OCF1
OC2R
OC1R
(Status Register) SR
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16-bit TIMERReal Time Clock

• In each Interrupt Routine the OCR Register
  content is updated.
• There is no shift time (the counter is never
  reset externally).

FREE RUNNING COUNTER VALUE
FFFFh
OCRDT
OCR
0000h
Timer IT
Timer IT
time
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16-bit TIMEROne pulse mode (1)

• Generation of a pulse synchronized with an
  external event
• Allows Phase Locked Loop Generation
• On Input Capture event
• The counter is reset
• The timer output pin is toggled
• On Output compare event
• The timer output pin is toggled
• The timer waits for the next Input Capture event

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16-bit TIMEROne pulse mode (2)
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16-bit TIMEROne pulse mode (3)
FREE RUNNING COUNTER VALUE
FFFFh
FFFCh
Compare 1
0000h
time
ICAP1 Input Capture pin Timer input
time
OCMP1 Ouput Compare pin Timer output
time
30
16-bit TIMERPWM mode (1)

• Automatic generation of a Pulse Width Modulated
  signal
• Period pulse lenght set by software
• The first Output Compare Register OC1R contains
  the length of the pulse
• The second Output Compare Register OCR2 contains
  the period of the pulse
• Resolution up to 100 steps at 20 KHz (fCPU 4
  MHz) 1 of accuracy on the duty cycle

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ST7 TIMERPWM mode (2)
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ST7 TIMERPWM mode (3)
FREE RUNNING COUNTER VALUE
Ttimer 65535
Tmax
FFFFh
FFFCh
Compare 2
Compare 1
0000h
time
OLVL2 1
OCMP1 Ouput Compare pin Timer output
OLVL10
time
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PROGRAMMING TIPS16-bit timer (1)

• Define Input capture pins as inputs through the
  corresponding Data Direction Register
• Read MSB first and then the LSB
• The counter LSB is buffered during the MSB read
• The counter LSB read accesses the buffered value
• Any access to the high byte disables the
  corresponding timer function until the low byte
  is accessed
• Disable the interrupts during any word access
• Writing the counter LSB resets the timer at FFFCh

34
PROGRAMMING TIPS16-bit timer (2)

• Clearing a status bit is performed by a read
  access to the status register followed by an
  access (read or write) to the low byte of the
  corresponding register
• The alternate counter register is always matching
  the counter
• Use the alternate counter register when you do
  not want to clear the Timer Overflow Flag
• No interrupt is generated on compare when the PWM
  is active, but the ICF1 bit is set every period
  and can generates an interrupt
• Be aware that the implicit reading performed by
  the emulator might clear the status flags

35
PROGRAMMING TIPS16-bit timer (3)
ACLR
36
Timer Configuration Example

• Fill the Timer registers in order to generate a
  real time clock at 5ms using an interrupt
  strategy a timer clock at 1µs (fCPU 8MHz).
• An interrupt is generated every 5ms using Output
  compare1.
• OCMP1 pin has to be toggled every period
• What is the value to add to the TAOC1HR TAOC1LR
  every period?

ICIE OCIE TOIE FOLVL2 FOLVL1 OLVL2 IEDG1 OLVL1
TACR1
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXED
TACR2
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Serial Peripheral Interface

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

38
ST7 SPIOverview

• THE SPI CELL ALLOWS A FULL DUPLEX SYNCHRONOUS
  SERIAL COMMUNICATION BETWEEN 2 DEVICES
• MAIN FEATURE
• Full duplex, 3 wire synchronous transfers
• Master 6 frequency available. It rates up to 2
  MHz
• Slave mode it rates up 4 MHz
• THE CLOCK IS PROGRAMMABLE POLARITY AND PHASE
• 3 DIFFERENT STATUS FLAG
• Data transfer data transfer completed
• Write collision access to SPIDR during a
  transmission
• Fault flag fault in master mode detected

39
ST7 SPIMaster-Slave communication
40
ST7 SPIBlock diagram
SPIDR
Read
Internal Bus
Read Buffer
IT

request
MISO
SPISR
MOSI
8-Bit Shift Register
MODF
-
SPIF
WCOL
-
-
-
-
Write
SPI STATE CONTROL
SCK
SPICR
MASTER CONTROL
MISCR2
SPR0
SPIE
SPE
SPR2-
MSTR
CPHA
SPR1
CPOL
SPIOD
SSM
SSI
SERIAL CLOCK GENERATOR
SS
41
ST7 SPISingle master configuration
SS
SS
SS
SS
SCK
SCK
SCK
SCK
Slave
Slave
Slave
Slave
MCU
MCU
MCU
MCU
MOSI
MOSI
MOSI
MOSI
MISO
MISO
MISO
MISO
MISO
MOSI
SCK
Master
MCU
5V
SS
42
SPI Configuration Example

• Fill the SPICR register in order to configure the
  SPI cell in
• Master mode
• Serial clock at 5OOKHz (fCPU8MHz)
• Sampling on 2nd edge
• High level after clock signal
• No interrupt generation

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
SPICR
43
ST7 I2C

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

44
ST7 I2C Overview

• The I2C cell provides all I2C bus specific
  sequencing, protocol, arbitration and timing in
  order to reduce as much as possible the software
  overhead
• Polling Management or Interrupt Driven Cell
• Main feature
• Multi Master capability
• Interrupt generation
• Standard I2C mode (up to 100kHz) and Fast I2C
  mode (up to 400kHz)
• 7-bit and 10-bit addressing

45
ST7 SCI

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

46
ST7 SCIOverview (1)

• FULL DUPLEX, ASYNCHRONOUS COMMUNICATION
• DUAL BAUD RATE GENERATOR (MAXIMUM SPEED FOR SCI
  TX and RX 250kHz)
• PROGRAMMABLE WORD LENGTH
• 8 bits
• 9 bits (8 bits of data plus parity bit)
• RECEIVER WAKE FUNCTION BY THE MOST SIGNIFICANT
  BIT OR IDLE LINE

47
ST7 SCIOverview (2)

• 3 FLAGS
• Buffer full
• Transmit buffer empty
• End of transmission
• MUTING FUNCTIONS FOR MULTIPROCESSOR
  CONFIGURATIONS
• NOISE, OVERRUN AND FRAME ERROR DETECTION
• 4 INTERRUPT SOURCES WITH FLAGS

48
ST7 SCISerial data format
49
SCI Sampling Data Format
Data Sampled values Received bit value NF Flag
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
Bit Time
Sampling Time

• Each bit time is
• Divided by 16 by the SCI clock
• Sampled 3 times on the 8th, 9th and 10th count of
  the SCI clock
• NF flag is set if the 3 sampling are not equal
  but the reception is still available

50
SCI Block Diagram
Data Register
51
ST7 SCI Clock selection
52
SCI Configurable Baud Rate
TR - SCT2SCT0 RR - SCR2SCR0 PR - SCP1,SCP0 ETPR /ERPR Baud Rate
64 - 110 13 - 11 0 300
16 - 100 13 - 11 0 1200
8 - 011 13 - 11 0 2400
4 - 010 13 - 11 0 4800
2 - 001 13 - 11 0 9600
8 - 011 3 - 01 0 10400
1 - 000 13 - 11 0 19000
X X 13 38000

• Values given for fCPU 8MHz
• PR selected by SCP1 SCP0 bits of SCIBRR Register
• TR selected by SCT2,SCT1 SCT0 bits of SCIBRR
  Register
• RR selected by SCR2,SCR1 SCR0 bits of SCIBRR
  Register
• Reach the industry standard requirement

53
SCI Configuration Example
R8 T8 M WAKE
SCICR1

• Fill the SCI registers in order to configure the
  Sci cell in
• 8 Bit word reception at 9600 Bauds
• 8 bit word transmission at 1200 Bauds
• Interrupt generation when RDRF is set (reception
  flag)
• fCPU 8MHz

TIE TCIE RIE ILIE TE RE RWU SBK
SCICR2
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
SCIBRR
54
ST7 EEPROM Data

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

55
SPGA Software Programable Gain Amplifier

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN

56
Programmable OpAmpOVERVIEW

• Integrated RAIL to RAIL OpAmp
• Internal low programmable Gain (Up to 16)
• Integrated reference voltage sources, VCC
  dependent independent (Band-Gap).
• OpAmp Outputs internally connected to ADC input
• Interupt flag in comparator mode
• Power on/off bit active in low power modes
• DAC capability with PWM/ART output

57
SPGABlock Diagram
SPGA1
To ADC Channel 8
58
SPGA MODES (1)
59
OPAMP MODES (2)
60
SPGA MODES (3)
61
ST7 CAN

• Optional features
• AD converter
• 16-bit Timer
• 8-bit Auto Reload Timer
• SPI
• SCI
• I2C
• EEPROM
• Programmable OpAmp
• CAN