Today: Verilog and Sequential Logic

1
Today Verilog and Sequential Logic

• Flip-flops
• representation of clocks - timing of state
  changes
• asynchronous vs. synchronous
• FSMs
• structural view (FFs separate from combinational
  logic)
• behavioral view (synthesis of sequencers)
• Sequential don't cares

2
Incorrect Flip-flop in Verilog

• Use always block's sensitivity list to wait for
  clock to change

module dff (CLK, d, q) input CLK, d output
q reg q always _at_(CLK) q d endmodule
Not correct! Q will change whenever the clock
changes, not just on the edge.
3
Correct Flip-flop in Verilog

• Use always block's sensitivity list to wait for
  clock edge

module dff (CLK, d, q) input CLK, d output
q reg q always _at_(posedge CLK) q
d endmodule
4
More Flip-flops

• Synchronous/asynchronous reset/set
• single thread that waits for the clock
• three parallel threads only one of which waits
  for the clock

Synchronous
Asynchronous
module dff (CLK, s, r, d, q) input CLK, s, r,
d output q reg q always _at_(posedge
CLK) if (r) q 1'b0 else if (s) q
1'b1 else q d endmodule
module dff (CLK, s, r, d, q) input CLK, s, r,
d output q reg q always _at_(posedge r) q
1'b0 always _at_(posedge s) q 1'b1 always
_at_(posedge CLK) q d endmodule
5
Example A parity checker

• Serial input string
• OUT1 if odd of 1s in input
• OUT0 if even of 1s in input

1. State diagram and state-transition table
Present Input Next
Present State State Output
Even 0 Even 0 Even 1
Odd 0 Odd 0 Odd 1 Odd
1 Even 1
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Example A parity checker (continued)

• 2. State minimization Already minimized
• Need both states (even and odd)
• Use one flip-flop
• 3. State assignment (or state encoding)

Present Input Next
Present State State Output
0 0 0 0 0 1
1 0 1 0 1 1 1
1 0 1
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Example A parity checker (continued)

• 4. Next-state logic minimization
• Assume D flip-flops
• Next state (present state) XOR (present input)
• Present output present state
• 5. Implement the design

8
Verilog Structural View of a FSM

• General view of a finite state machine in verilog

module FSM (CLK, in, out) input CLK input in
output out reg out // state variable
reg 10 state // local variable reg
10 next_state always _at_(posedge CLK) //
registers state next_state always _at_(state
or in) // Compute next-state and output logic
whenever state or inputs change. // (i.e. put
equations here for next_state10) // Make
sure every local variable has an assignment in
this block!endmodule
9
Moore Verilog FSM

• Reduce 1s example

define zero 0define one1 1define two1s
2module reduce (CLK, reset, in, out) input
CLK, reset, in output out reg out reg
10 state // state variables reg 10
next_state always _at_(posedge CLK) if
(reset) state zero else state
next_state
state assignment
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Moore Verilog FSM (continued)
always _at_(in or state) case (state)
zero // last input was a zero begin
if (in) next_state one1 else
next_state zero end one1 //
we've seen one 1 begin if (in)
next_state two1s else next_state
zero end two1s // we've seen
at least 2 ones begin if (in)
next_state two1s else next_state
zero end endcase
crucial to include all signals that are input
to state and output equations
note that output onlydepends on state
always _at_(state) case (state) zero
out 0 one1 out 0 two1s out 1
endcase endmodule
11
Mealy Verilog FSM
module reduce (CLK, reset, in, out) input CLK,
reset, in output out reg out reg
state // state variables reg next_state
always _at_(posedge CLK) if (reset) state
zero else state next_state
always _at_(in or state) case (state)
zero // last input was a zero begin
out 0 if (in) next_state one
else next_state zero end
one // we've seen one 1 if (in) begin
next_state one out 1 end
else begin next_state zero out
0 end endcaseendmodule
Remember the Highlight- The-Arrows Method
Input
Output
12
Blocking and Non-Blocking Assignments

• Blocking assignments (XA)
• completes the assignment before continuing on to
  next statement
• Non-blocking assignments (XltA)
• completes in zero time and doesnt change the
  value of the target until a blocking point
  (delay/wait) is encountered
• Example swap

always _at_(posedge CLK) begin temp B B
A A temp end
always _at_(posedge CLK) begin A lt B B lt
A end
13
RTL Assignment

• Non-blocking assignment is also known as an RTL
  assignment
• if used in an always block triggered by a clock
  edge
• mimic register-transfer-level semantics  all
  flip-flops change together

// B,C,D all get the value of Aalways _at_(posedge
clk) begin B A C B D
C end
// this implements a shift registeralways
_at_(posedge clk) begin D, C, B C, B,
A end
// implements a shift register tooalways
_at_(posedge clk) begin B lt A C lt
B D lt C end