A ZVS approach for AC/DC converter with PFC

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A ZVS approach for AC/DC converter with PFC

• PowereLab HKU

The Power Electronics Lab., Hong Kong
University N. K. Poon C. P. Liu M. H. Pong
Speaker Bryan M. H. Pong
Prepared by Franki Poon
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Some basic concepts

• Input rectifiers and capacitor produce Pulsating
  input current
• Harmonic currents are generated

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A conventional method

• A boost converter and a DC/DC converter

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A popular method among researchers

• Single stage design which combines the boost and
  the DCDC converters

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Is single stage design always better?

• Let us take a look

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Why two-stage design?

• Advantage
• Losses ? Ipfc2 Idc2
• Fix DCDC input voltage
• Controllable bulk voltage
• Disadvantage
• Need two controllers
• One more MOSFET

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Why single-stage design?

• Advantage
• One controller
• One MOSFET less
• Disadvantage
• Losses ? (Ipfc Idc)2
• High Idc at low line
• Higher Ipfc
• High current stress
• High voltage stress

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Good reasons for two-stage

• Single Stage
• Advantages
• One controller
• One MOSFET less
• Disadvantages
• Losses ? (Ipfc Idc)2
• High Idc at low line
• Higher Ipfc
• High current stress
• High voltage stress

• Two-Stage
• Advantages
• Losses ? Ipfc2 Idc2
• Fix DCDC input voltage
• Controllable bulk voltage
• Disadvantages
• Need two controller
• One more MOSFET

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Our new idea Boost Asymmetric half-bridge with
soft switching
DMpfc gt DM2
M1
Mpfc
M2
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Zero voltage state - M2
M1 turn off then . .
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Zero voltage state - Mpfc
After M2 turn on
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Two separate converters
M2 turn on Mpfc turn on
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Zero voltage state M1
M2 turn off Mpfc turn on
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One cycle on asymmetric
M1 turn on Mpfc turn on
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One cycle on PFC
M1 turn on Mpfc turn off
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Its great, but . . .
If DMpfc lt DM2 DMpfc DM2
No control for PFC !!
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After all small Maux added
For all DMpfc and all DM2
M1
Maux
Mpfc
M2
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Final timing arrangement
ZVS too
M2 gate drive
A
M1 gate drive
B
Maux gate drive
Mpfc gate drive
VA VB VMaux_ds VA-VB 0
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Practical consideration
M1
Maux
Mpfc
Doff
M2
guarantee a path for Laux current when M2 off at
any time
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Practical circuit O/P 12V_at_10A
250uH
IRF840A
Two diodes are used to clamp ringing
STD5NM50
12uH
8uH
STPS12NM50
STPS12NM50
Active Diode
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Simplified timing circuit
L5991
M2 gate
O/P
Sync
M1 gate
Maux gate
Sync
L4981
Mpfc gate
O/P
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How does it look?
A 120W, 12V10A AC adapter
Width 12.6cm Depth 6.3cm Height 1.9cm
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ZVS on M2
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ZVS on Mpfc
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ZVS on Mpfc M2
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Losses and Efficiency
91 efficiency 12V_at_10A
lt 1W at no load
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Finally . . .

• Simple Boost Asymmetric Half-bridge
  configuration Good Combination.
• All ZVS behaviors Very little added cost.
• Two separate converter Easy to control
• Active diode can be incorporated lt1W no load
  power
• Simple PWM controller simple ASIC

Prepared by Franki Poon
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