Combinational Logic and Verilog

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Combinational Logic and Verilog
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• Programmable Array Logic
• PAL

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Example of PAL. GAL16V8C
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PALs

1. SOP
2. Multi-level
3. Flip-flops
4. 10 Inputs
5. 8 Inputs/output

Figure 6-26. PAL16L8
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Figure 6-28. General CPLD architecture
Complex PLD
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43 PLA in CMOS logic
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EEPLDs

• Floating gate
• Non-floating gate

AND plane of EEPLD using floating-gate MOS
transistors
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• Decoders

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General Structure of a Decoder circuit
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Example 1 Truth table for a 2-to-4 binary
decoder.
Example of a decoder circuit
enable
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2-to-4 decoder inside
enable
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Verilog for 2-to-4 decoder
Structural type of description in Verilog
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Example 2 Position encoding for a 3-bit
mechanical encoding disk
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Example 2 continued Using a 3-to-8 decoder to
decode a Gray code.
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Example 3 74x138 3-to-8 decoder
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Example 3 74x138 3-to-8 decoder
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Example 3 cont 74X138 3-to-8 decoder
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Verilog code for 3-to-8 decoder
15..7
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Verilog for 3-to-8 decoder
Y_L0 Y_L1 Y_L2 Y_L3 Y_L4 Y_L5 Y_L7
A2 A1 A0
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74X138 Decoder Active level handling
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74x138 like decoder with Active level handling
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Active high 3-to-8 decoder
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Behavioral Verilog for 3-to-8 decoder
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Example 3 cont 74x138 3-to-8 decoder
Default signal names
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Example 3 cont Symbols for 74x138
Incorrect because of double negations
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Example 3 cont 5-to-32 decoder from 74X138 chips
Chip select goes to input G2B
Global enable goes to inputs G1 and G2A
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Example 3 cont 4-to-16 decoder using 74X138
N3
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Example 3 cont 74x138 decoder using GAL
74x138 decoder can be built in single GAL 16V8
chip
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Figure 6-41. 74x138-like decoder
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Example Customized decoder function
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Customized decoder circuit Using 74X138
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• Seven Segment Display and Decoder

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Seven Segment Display
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Seven Segment Decoder
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Encoders
We already used encoders to design control logic
for data path blocks
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Encoders
2n requests
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• Priority Encoders

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Encoders
Number n of prioritized request
Any subset if 2n requests
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Encoders
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8-input Priority Encoder
enable
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15-input Priority Encoder in PLD
outputs
inputs
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Priority Encoder handle 32 requests
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8-input Priority Encoder
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• Three state
• Buffers

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Various three-state buffers
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Use of three-state buffers
Eight sources sharing a three-state party line
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Timing diagram for the three-state party line
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74x541 Octal three-state buffer
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• Three-State buffers in microprocessors

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74x541 as a microprocessor input port.
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Verilog module for a 74x540-like 8-bit
three-state driver
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74x245 octal three-state transceiver
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Verilog module for a 74x245-like 8-bit transceiver
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Bidirectional buses and transceiver operation
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Bus selection codes for a four-way bus transceiver
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PLD inputs and outputs for a four-way, 2-bit bus
transceiver
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Verilog module for a four-way, 2-bit bus
transceiver
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• Multiplexers

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Multiplexer structure
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74x151 8-input, 1-bit mux
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74x151 8-input, 1-bit mux
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Combining 74x151s to make a 32-to-1 multiplexer
Decoding and enabling
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74x157 2-input 4-bit mux
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GAL16V8 used as a 74x157 multiplexer
2 inputs, each 4 bits
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Buffers to handle large fanout
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A mux driving a bus and a demux receiving the bus
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• Decoders as demultiplexers

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3-to-8 binary decoder as a demultiplexer
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• GALs as multiplexers

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Function table for a SPECIALIZED 4-input, 18-bit
mux.
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Behavioral Verilog for a specialized 4-input
18-bit mux
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Dataflow Verilog for a 4-input, 8-bit mux
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Behavioral Verilog for a 4-input, 8-bit mux.