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Chameleon Chip

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Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves. – PowerPoint PPT presentation

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Title: Chameleon Chip


1
Chameleon Chip
2
Topics Covered
1.Introduction 2.Multifunction Implementation 3.Th
e General Architecture Of Reconfigurable
Processor 4.Architecture 5.Reconfigurable
Processing Fabric 6.Programmable
I/O 7.Technologies Used In Chip 8.Design
Process 9.Comparison With Other
Technologies 10.Advantages 11.Disadvantages 12.App
lications 13.References 14.Conclusion
3
1.Introduction
  • A reconfigurable processor is a microprocessor
    with erasable hardware that can rewire itself
    Dynamically.
  • This allows the chip to adapt effectively to the
    programming tasks demanded by the particular
    software they are interfacing with at any given
    time.
  • Reconfigurable processor chip usually contains
    several parallel processing computational units
    known as functional blocks.
  • While reconfiguring the chip, the connections
    inside the functional blocks and the connections
    in between the functional blocks are changing,
  • that means when a particular software is
    loaded the present hardware design is erased and
    a new hardware design is generated by making a
    particular number of connections active while
    making others idle.

4
  • This will define the optimum hardware
    configuration for that particular software.
  • It takes just 20 microseconds to reconfigure the
    entire processing array.
  • Reconfigurable processors are currently available
    from Chameleon Systems, Billions of Operations
    (BOPS), and PACT (Parallel Array Computing
    Technology).
  • Among those only Chameleon is providing a design
    environment, which allows customers to convert
    their algorithms to hardware configuration by
    themselves. 

5
2.Multifunction Implementation
  • In a conventional ASIC or FPGA, multiple
    algorithms are implemented as separate hardware
    modules. Four algorithms would divide the chip
    into four functional areas.
  • With Reconfigurable Technology, the four
    algorithms are loaded into the entire
    reconfigurable Fabric one at a time. First, the
    entire Fabric is dedicated to algorithm 1 during
    this processing time, algorithm 2 is loaded into
    the background place. In a single clock cycle,
    the entire Fabric is swapped to algorithm 2
    during this processing time, algorithm 3 is
    loaded into the background plane. The entire
    reconfigurable fabric is dedicated to just one
    algorithm at a time.
  • So finally the result is much higher
    performance, lower cost and lower power
    consumption

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7
3.The General Architecture Of Reconfigurable
Processor
  • Machine design supposes that some pins are
    considered as the configuration inputs and
    another as data or control inputs and outputs.
  • A new chip must inside determine the set of the
    function blocks (FB), which are used to construct
    the circuit, rules of their interconnections and
    ways of the input/output connections.
  • The most important parts are the logic circuits,
    which configure function blocks according to data
    in the configuration memory.
  • The various possible connections between
    functional blocks are encoded to bits known as
    Configuration bits. Resulting configuration
    stream is downloaded into configuration memory
    through configuration inputs.
  • Thus, a new Reconfigurable machine is
    established.

8
4.Architecture
  • Components
  • 32-bit Risc ARC processor _at_125MHz
  • 64 bit memory controller
  • 32 bit PCI controller
  • reconfigurable processing fabric (RPF)
  • high speed system bus
  • programmable I/O (160 pins)
  • DMA Subsystem
  • Configuration Subsystem

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10
5.Reconfigurable Processing Fabric(RPF)
  • The Fabric provides unmatched algorithmic
    computation power to Chameleon Chip. It consists
    of 84,32-bit Data path Units and 24, 1624-bit
    Multipliers,Operating at 125Mhz, they provide up
    to 3,000 16-bit Million Multiply-Accumulates Per
    Second and 24,000 16-bit Million Operations Per
    Second.
  • The fabric is divided into Slices, the basic unit
    of reconfiguration.
  • The CS2112 has 4 Slices with 3 Tiles in each.
    Each tile can be reconfigured at runtime
  • Tiles contain
  • Datapath Units
  • Local Store Memories
  • 16x24 multipliers
  • Control Logic Unit

11
  • The high-performance 32bit Data path Unit (DPU)
    The Tile includes seven Data path Units. The DPU
    is a data processing module that directly
    supports all C and Verilog operations.

12
6.Programmable I/O
  • RCP includes banks of Programmable I/O (PIO) pins
    which provide tremendous bandwidth.
  • Each PIO bank of 40 PIO pins delivers 0.5
    GBytes/sec I/O bandwidth.

7.Technologies Used In Chip 1. eCONFIGURABLE
TECHNOLOGY This technology reconfigures fabric
in one clock cycle and increases voice/data/video
channels per chip. As mentioned earlier, each
Slice can be configured independently. Loading
the Background Plane from external memory
requires just 3 µsec per Slice this operation
does not interfere with active processing on the
Fabric. Swapping the Background Plane into the
Active Plane requires just one clock cycle. with
eConfigurable Technology the four algorithms are
loaded into the entire reconfigurable processing
Fabric one at a time. 
13
  • 2. CSIDE Development Tools
  • With this software development tool , Chameleon
    Systems are providing the ability for the
    customers to do the programming themselves thus
    keeping the secrecy of their algorithms.
  • The Chameleon Systems Integrated Development
    Environment (CSIDE) is a complete toolkit for
    designing, debugging and verifying RCP designs.
  • CSide uses a combined C language and Verilog
    flow to map algorithms into the chips
    reconfigurable processing fabric (RPF).
  • 3. eBIOS 
  • It provides a interface between the Embedded
    Processor System and the Fabric.
  • eBIOS provides resource allocation, configuration
    management and DMA services.
  • The eBIOS calls are automatically generated at
    compile time, but can be edited for precise
    control of any function. 

14
8.Design Process
15
9.Comparison With Other Technologies
  • Todays system architects have at their disposal
    an arsenal of highly integrated, high-performance
    semiconductor technologies, such as
    application-specific integrated circuits (ASICs),
    application-specific standard products (ASSPs),
    digital signal processors (DSPs), and
    field-programmable gate arrays (FPGAs). However,
    system architects continue to struggle with the
    requirement that communication systems deliver
    both performance and flexibility.
  • The reconfigurable processor, an entirely new
    category of semiconductor solution that serves as
    a system-level platform for a broad range of
    applications.

16
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17
10.Advantages
  • can create customized communications signal
    processors
  • increased performance and channel count
  • can more quickly adapt to new requirements and
    standards
  • lower development costs and reduce risk.
  • Reducing power
  • Reducing manufacturing cost.

18
11.Disadvantages
  • Inertia  Engineers slow to change
  • Inertia is the worst problem facing
    reconfigurable computing
  • RCP designs requires comprehensive set of tools
  • 'Learning curve' for designers unfamiliar with
  • reconfigurable logic 

19
12.Applications
  • Wireless Base stations- The reconfigurable
    technology mainly focuses on base stations and
    their unpredictable combination of voice and data
    traffic.Base-station infrastructure will have to
    be adaptive enough to accommodate those
    requirements. With a fixed processor the channels
    must be able to support both simple voice calls
    and high-bandwidth data connections
  • Wireless Local Loop (WLL)- Reconfigurable
    technology is widely applied in Wireless
    Local Loops also because of their high processing
    power, bandwidth and reconfigurable nature.
  • High-Performance DSL (Digital Subscriber Line
    Technology)- DSL technology brings high Bandwidth
    to homely users.
  • Software-Defined Radio (SDR)- SDR concept is
    applied in Cell phone Technology

20
13.Conclusion These new chips called chameleon
chips are able to rewire themselves on the fly
to create the exact hardware needed to run a
piece of software at the outmost speed. Its
applications are in, data-intensive
Internet,DSP,wireless basestations, voice
compression, software-defined radio,
high-performance embedded telecom and datacom
applications, xDSL concentrators,fixed wireless
local loop, multichannel voice compression,
multiprotocol packet and cell processing
protocols. Its advantages are that it can
create customized communications signal
processors ,it has increased performance and
channel count, and it can more quickly adapt to
new requirements and standards and it has lower
development costs and reduce risk.
21
References
  • Wei Qin Presentation , Oct 2000 (The part of the
    presentation regarding
  • CS2000 is covered in this page)
  • IEEE conference on Tele-communication, 2001.
  •  
  •  
  • WEBSITES
  • www.chameleonsystems.com
  • www.thinkdigit.com
  • www.ieee.org
  • www.entecollege.com
  • www.iec.org
  • www.quicksilver technologies.com
  • www.xilinx.com

22
THANK YOU
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